Analog Layout Engineer

Inabia Solutions and Consulting, Inc.

. Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits such as SerDes, ADCs, DACs, PLLs, and high-speed blocks .

Posted 11/4/2026contractRemote • Texas • United StatesSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in designing physical silicon layouts for high-frequency mixed-signal circuits, with a strong focus on high-speed analog layout, floor planning, and integration. Proficient in addressing layout-dependent effects and ensuring compliance with DRC, LVS, and ESD protection standards.

Highest-signal resume keywords

Custom IC Layout ExperienceHigh-Speed Analog LayoutTSMC 4NM ExperienceFloor Planning and IntegrationLayout-Dependent Effects Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Silicon Layout DesignMixed-Signal CircuitsHigh-Speed BlocksHierarchical Block IntegrationMicro-Bump Co-DesignDRC ComplianceLVS ComplianceERC ComplianceEM/IR ReliabilityESD Protection

Industry Keywords

Deep Sub-MicronCMOSFinFETN3 NodeN5 NodeDevice MatchingCommon-Centroid StructuresGuard RingsIsolationShielding

About the role

Key responsibilities & impact

Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits such as SerDes, ADCs, DACs, PLLs, and high-speed blocks
Create block-level and chip-top-level floor plans
Manage hierarchical block integration
Handle micro-bump or package-aware co-design
Address layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding
Ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

Requirements

What you’ll need

7+ years of relevant experience
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes
Experience at lower nodes (N3, N5) is critical
TSMC 4NM experience is a must-have
High-speed analog layout experience
Experience with floor planning and integration, including block-level and chip-top-level floor plans, hierarchical block integration, and micro-bump or package-aware co-design
Knowledge of layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding
Experience with DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection
Must be eligible to work under the stated visa requirements; H1B transfers are excluded

Benefits

Comp & perks

Contracted employment
All visa types accepted except H1B transfer
C2C engagements are allowed