Analog Layout Engineer

Inabia Solutions and Consulting, Inc.

. Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits .

Posted 11/4/2026contractRemote • Texas • United StatesSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in designing physical silicon layouts for high-frequency mixed-signal circuits, with a strong focus on high-speed analog layout and advanced CMOS/FinFET nodes. Proficient in managing hierarchical block integration and ensuring compliance with layout-dependent effects and reliability standards.

Highest-signal resume keywords

High-Speed Analog LayoutCustom IC Layout ExperienceTSMC 4NM ExperienceHierarchical Block IntegrationDRC, LVS, ERC Compliance

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical Silicon Layout DesignMixed-Signal Circuit DesignBlock-Level Floor PlanningChip-Top-Level Floor PlanningMicro-Bump Co-DesignLayout-Dependent Effects KnowledgeDevice MatchingGuard RingsEM/IR ReliabilityESD Protection

Industry Keywords

Deep Sub-MicronCMOSFinFETSerDesADCsDACsPLLsAntenna RulesIsolationShielding

About the role

Key responsibilities & impact

Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits
Create block-level and chip-top-level floor plans
Manage hierarchical block integration
Handle micro-bump or package-aware co-design
Address layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding
Ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

Requirements

What you’ll need

7+ years of relevant experience required
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes
Experience at lower nodes (N3, N5) is critical
TSMC 4NM experience is a must-have
Expertise in high-speed analog layout for mixed-signal circuits such as SerDes, ADCs, DACs, PLLs, and high-speed blocks
Experience with block-level and chip-top-level floor planning
Experience managing hierarchical block integration
Experience with micro-bump or package-aware co-design
Knowledge of layout-dependent effects (LOD, WPE, LDE)
Knowledge of device matching and common-centroid structures
Experience with guard rings and isolation or shielding, including coaxial, differential, and ground shields
Experience ensuring closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection
Must be authorized to work under an eligible visa status; H1B transfers are excluded

Benefits

Comp & perks

Remote work arrangement
Contract engagement
All visa types accepted except H1B transfer
C2C engagements are allowed