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Inabia Solutions and Consulting, Inc.

IP Integration Engineer

Inabia Solutions and Consulting, Inc.

. Integrate subsystems or SoCs .

Posted 11/5/2026full-timeRemote • United StatesSeniorLeadWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive expertise in Subsystem and SoC Integration, with a strong focus on Verilog/SystemVerilog, IP Integration, and Design-Quality Closure. Proven ability to optimize performance and ensure customer satisfaction through effective communication and problem-solving.

Highest-signal resume keywords
Verilog/SystemVerilog ExperienceSubsystem IntegrationIP IntegrationDesign-Quality ClosurePerformance Optimization

ATS Keywords

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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills
Subsystem IntegrationSoC IntegrationVerilogSystemVerilogSynthesis ConstraintsTiming ConstraintsFloor-PlanningPerformance OptimizationDesign-Quality ClosureRegister Integration
Soft Skills
Problem SolvingIndependent WorkResource for ColleaguesProcess ImprovementCustomer Satisfaction
Industry Keywords
1P IP3P IPCDCLintRDCRTL DesignDigital Concepts

About the role

Key responsibilities & impact
  • Integrate subsystems or SoCs
  • Integrate 1P and 3P IPs
  • Generate 3P fabrics
  • Perform quality checks and PD handoff
  • Conduct subsystem integration using Verilog/SystemVerilog
  • Apply synthesis and timing constraints
  • Consider floor-planning requirements
  • Optimize performance
  • Complete design-quality closure, including CDC, Lint, and RDC
  • Perform register integration
  • Ensure customer satisfaction
  • Report progress to customers daily or weekly

Requirements

What you’ll need
  • 7+ years of relevant experience stated for the role
  • In-depth knowledge and experience
  • Ability to solve complex problems using existing solutions
  • Ability to work independently with minimal guidance
  • Ability to serve as a resource for less experienced colleagues
  • Ability to contribute to process improvements
  • Verilog/SystemVerilog experience
  • RTL design and digital concepts knowledge
  • Subsystem or SoC integration experience
  • IP integration, including 1P and 3P IPs
  • Synthesis and timing constraints
  • Floor-planning considerations
  • Performance optimization
  • Design-quality closure, including CDC, Lint, and RDC
  • Register integration
  • Typically requires 5–7 years of related experience with a 4-year degree; or 3 years and an advanced degree; or equivalent work experience

Benefits

Comp & perks
  • Remote work arrangement