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Inabia Solutions and Consulting, Inc.

RTL Design – Integration Engineer

Inabia Solutions and Consulting, Inc.

. Design and integrate RTL and digital subsystems .

Posted 11/4/2026contractRemote • United StatesSeniorLeadWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive expertise in RTL design and digital subsystem integration, with a strong focus on Verilog/SystemVerilog, performance optimization, and quality assurance. Proven ability to manage customer relationships and guide junior staff while contributing to process improvements.

Highest-signal resume keywords
RTL DesignVerilog/SystemVerilogSubsystem IntegrationPerformance OptimizationCDC, Lint, RDC Integration

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
RTL DesignVerilogSystemVerilogSubsystem IntegrationSynthesisTiming ConstraintsFloor-PlanningPerformance OptimizationDesign-Quality ClosureRegister Integration
Soft Skills
Customer SatisfactionIndependent WorkInformal Guidance
Industry Keywords
Digital SubsystemsFirst-Party IPThird-Party IP3P FabricsProcess Improvements

About the role

Key responsibilities & impact
  • Design and integrate RTL and digital subsystems
  • Integrate first-party and third-party IPs
  • Generate third-party fabrics and perform quality checks
  • Support physical-design handoff
  • Perform subsystem integration using Verilog/SystemVerilog
  • Address synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure
  • Perform CDC, Lint, RDC, and register integration
  • Ensure customer satisfaction
  • Report progress to customers daily or weekly
  • Work independently with minimal guidance
  • Provide informal guidance to junior staff
  • Contribute to process improvements

Requirements

What you’ll need
  • 7+ years of relevant experience
  • In-depth knowledge and experience in RTL design and digital concepts
  • Experience with subsystem or SoC integration
  • Experience integrating 1P and 3P IPs and generating 3P fabrics
  • Experience with Verilog/SystemVerilog
  • Experience with synthesis and timing constraints
  • Knowledge of floor-planning considerations
  • Experience with performance optimization and design-quality closure
  • Experience with CDC, Lint, RDC, and register integration
  • Typically requires 5–7 years of related experience with a 4-year degree; or 3 years and an advanced degree; or equivalent work experience
  • All visas accepted except H1B transfer