FREE ACCESS
5,000–10,000 jobs/day
See all jobs on Scoutfield
Search thousands of fresh jobs every day.
Discover
- Fresh listings
- Fast filters
- No subscription required
Create a free account and start exploring right away.
RTL Design – Integration Engineer
Inabia Solutions and Consulting, Inc.. Perform RTL design and integration .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates extensive expertise in RTL design, subsystem integration, and performance optimization, with a strong focus on quality assurance and customer satisfaction. Proficient in Verilog/SystemVerilog and familiar with design-quality closure methodologies including CDC, Lint, and RDC.
Highest-signal resume keywords
RTL DesignSubsystem IntegrationVerilog/SystemVerilogPerformance OptimizationDesign-Quality Closure
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
RTL DesignSubsystem IntegrationVerilogSystemVerilogSynthesisTiming ConstraintsPerformance OptimizationDesign-Quality ClosureCDCLint
Soft Skills
Customer SatisfactionIndependent WorkInformal GuidanceProcess Improvements
Tools & Technologies
3P Fabrics1P IPs3P IPs
Industry Keywords
Digital ConceptsFloor-PlanningQuality ChecksPD HandoffRegister Integration
About the role
Key responsibilities & impact- Perform RTL design and integration
- Integrate subsystems or SoCs
- Integrate 1P and 3P IPs
- Generate 3P fabrics
- Perform quality checks and PD handoff
- Conduct subsystem integration using Verilog/SystemVerilog
- Handle synthesis and timing constraints
- Consider floor-planning requirements
- Optimize performance
- Drive design-quality closure, including CDC, Lint, and RDC
- Integrate registers
- Ensure customer satisfaction
- Report progress to customers daily or weekly
Requirements
What you’ll need- 7+ years of relevant experience
- In-depth knowledge and experience
- Understanding of RTL design and digital concepts
- Experience with subsystem or SoC integration
- Experience integrating 1P and 3P IPs
- Experience generating 3P fabrics, quality checks, and PD handoff
- Experience with Verilog/SystemVerilog
- Knowledge of synthesis and timing constraints
- Understanding of floor-planning considerations
- Experience with performance optimization and design-quality closure
- Experience with CDC, Lint, RDC, and register integration
- Ability to work independently with minimal guidance
- Typically requires 5–7 years of related experience with a 4-year degree; or 3 years and an advanced degree; or equivalent work experience
- Ability to provide informal guidance to junior staff
- Ability to contribute to process improvements
Benefits
Comp & perks- C2C engagements are allowed
- All visas are accepted except H1B transfer
- Remote work arrangement