3DIC Device Development Engineer

Intel Corporation

. Characterize and model the impact of advanced 3D integration technologies on device performance metrics including mobility, threshold voltage, leakage, matching, and variability .

Posted 11/11/2026full-timeUnited StatesMid-LevelSenior💰 $136,900 - $269,150 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in advanced CMOS device characterization, including electrical parametric data analysis and the impact of thermal and stress interactions on device performance. Proficient in collaborating across multiple engineering disciplines to drive technology qualification and manufacturing readiness in semiconductor environments.

Highest-signal resume keywords

Advanced CMOS Device CharacterizationElectrical Parametric Data AnalysisTest Structure Development3D Integration TechnologiesDevice Modeling and Design Rule Development

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Device CharacterizationElectrical TestingStatistical AnalysisData ScienceScripting CapabilitiesDesign of Experiments (DOE)Device PhysicsSemiconductor Reliability MechanismsFinFET and GAA DevicesTechnology Transfer

Soft Skills

Analytical SkillsProblem-Solving SkillsCommunication SkillsCollaboration SkillsInfluencing Skills

Tools & Technologies

TCADFinite Element Analysis Tools3D Design KitsPDK GenerationE-Test Program Implementation

Industry Keywords

Semiconductor Device EngineeringProcess IntegrationAdvanced PackagingHigh-Speed I/O DevicesCustomer Engagement

Tech Stack

Tools & technologies

Assembly

About the role

Key responsibilities & impact

Characterize and model the impact of advanced 3D integration technologies on device performance metrics including mobility, threshold voltage, leakage, matching, and variability
Evaluate stress, thermal, and electrical coupling effects, including keep-out zone behavior and device interactions within complex 3D stacks
Define and develop device and passive test structures, including TSV proximity, KOZ, guard ring, resistor, and capacitor structures
Drive electrical test strategy, data collection, and silicon analysis
Provide device characterization inputs for design rules, compact models, PDKs, and 3D design kit releases
Collaborate with Process Integration, Packaging, Assembly, Reliability, Yield, and Program Management teams
Evaluate customer requirements for analog, mixed-signal, RF, and high-speed I/O devices in 3D architectures
Support technology qualification and manufacturing readiness, including device targeting, monitoring strategies, yield improvement, and excursion management
Communicate technical findings and recommendations to engineering, business, and customer stakeholders

Requirements

What you’ll need

Master's degree in Electrical Engineering, Physics, Materials Science, or a related field
4+ years of industry experience in semiconductor device engineering, process integration, advanced packaging, or related technology development
3+ years of experience in advanced CMOS device characterization and electrical parametric (e-test) data analysis
Hands-on experience with one or more advanced packaging and 3D integration technologies, including through-silicon vias (TSVs), hybrid bonding, wafer-to-wafer or die-to-wafer bonding, micro-bump technologies, wafer thinning, or backside power delivery
Deep understanding of CMOS device physics and the impact of process, stress, and thermal effects on device performance
Strong analytical and problem-solving skills, including data science, statistical analysis, and scripting capabilities
Excellent written and verbal communication skills
Proven ability to influence and collaborate across device, process, packaging, manufacturing, and design organizations
Preferred: PhD in Electrical Engineering, Physics, Materials Science, or a related field
Experience analyzing stress and thermal interactions affecting device behavior, including TSV keep-out zones and chip-package interaction effects
Expertise in test structure development, design of experiments (DOE), and e-test program implementation
Knowledge of device modeling, design rule development, PDK generation, or design technology co-optimization (DTCO)
Experience using TCAD and/or finite element analysis tools
Understanding of semiconductor reliability mechanisms, including EM, TDDB, BTI, and bonding interface reliability
Experience with FinFET and GAA devices
Semiconductor foundry experience with direct customer engagement and technical support
Experience supporting technology transfer and production ramp in high-volume manufacturing environments

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site at their assigned Intel site and off-site