AI GPU Cache Designer

Intel Corporation

. Develop Cache subsystem designs for Intel's AI SoCs .

Posted 9/28/2026full-timeUnited StatesMid-LevelSenior💰 $220,920 - $311,890 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates advanced proficiency in RTL design using Verilog/SystemVerilog, with extensive experience in SoC development, microarchitecture specifications, and subsystem integration. Capable of leading silicon bring-up and post-silicon validation while mentoring junior engineers and enhancing design methodologies.

Highest-signal resume keywords

RTL Design Using Verilog/SystemVerilogSoC System IntegrationStandard Bus Protocols (AXI, AHB)Scripting Languages (Python, TCL)High-Speed and Low-Power Design Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignMicroarchitecture SpecificationSubsystem IntegrationTiming ClosurePower OptimizationClock Domain CrossingSoC Multicore CPU Subsystem DesignGPU Cache DevelopmentSimulation ProcessesDebugging

Soft Skills

MentoringCollaboration

Tools & Technologies

HDL Simulators (VCS, Questa, IES)Lint Tools (Spyglass)FPGA Prototyping Tools (Xilinx Vivado, Altera Quartus II)

Industry Keywords

ASIC DevelopmentSoC DevelopmentDesign MethodologyQuality AssuranceBackground Investigation

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop Cache subsystem designs for Intel's AI SoCs
Drive microarchitecture, RTL coding, subsystem integration, and simulation processes
Evaluate architectural trade-offs against performance, power, and system constraints
Define and document microarchitecture specifications for complex SoC IP blocks
Implement RTL in Verilog/SystemVerilog and deliver synthesis- and timing-clean designs
Collaborate with verification teams on validation and coverage
Develop and maintain timing constraints for IP blocks
Support physical design teams with synthesis, timing closure, and formal equivalence checks
Lead silicon bring-up, post-silicon validation, debugging, and performance analysis
Mentor junior engineers and advance design methodology and quality assurance practices

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in a relevant field with 8+ years of experience; OR PhD in a relevant field with 6+ years of experience
Advanced proficiency in RTL design using Verilog/SystemVerilog
Hands-on experience in SoC system integration
Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures
Ability to address clock domain crossings, power optimization, and timing closure
Proficiency in scripting languages such as Python and TCL
Strong knowledge of high-speed and low-power design techniques
Familiarity with HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II)
Experience in SoC multicore CPU subsystem design and GPU cache development
Must consent to and pass an extended Background Investigation

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation