CPU Clock Design Engineer

Intel Corporation

. Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products .

Posted 10/6/2026full-timeUnited StatesMid-LevelSenior💰 $105,650 - $269,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in clock distribution network design, clock tree synthesis methodologies, and timing analysis for high-performance CPU and SoC products. Proficient in developing custom circuits and automation solutions while collaborating effectively across multidisciplinary teams.

Highest-signal resume keywords

Clock Distribution Network DesignClock Tree Synthesis (CTS)Static Timing Analysis (STA)Digital Circuit DesignProgramming in Python, Perl, TCL, or Shell

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Clock Distribution Network DesignClock Tree Synthesis (CTS)Static Timing Analysis (STA)Digital Circuit DesignCustom Circuit DesignTiming Closure MethodologiesVLSI DesignPhysical DesignLogic DesignSemiconductor Design Methodologies

Soft Skills

CollaborationProblem-SolvingTechnical Issue Resolution

Tools & Technologies

EDA ToolsFull-Chip Design Tools

Industry Keywords

High-Performance CPUSoC ProductsClocking ArchitecturePLL/DLL ArchitectureTiming Constraint Adaptation

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products
Contribute to clock architecture development and clock tree synthesis methodologies
Perform timing analysis and support timing closure across complex semiconductor designs
Develop custom circuits, library cells, and clock-related design solutions
Analyze performance, power, area, and timing tradeoffs
Create automation solutions using scripting and programming languages
Collaborate with architecture, design, physical implementation, validation, and EDA teams
Support debug, validation, and optimization throughout the product development lifecycle
Drive technical issues to closure while maintaining high-quality engineering standards
Influence future methodologies, design flows, and clocking technologies

Requirements

What you’ll need

Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related STEM field with 3+ years of experience, or a Master's degree in the same field with 1+ years of educational or work experience
Experience in three or more of: Digital circuit design, VLSI design, physical design, clock tree synthesis (CTS), static timing analysis (STA), logic design, custom circuit design, semiconductor design methodologies
Experience with one or more programming or scripting languages such as Python, Perl, TCL, Shell, or similar
Preferred: PhD in Electrical/Computer Engineering or related field
Preferred: Hands-on experience in high-frequency custom clock network design on leading-edge technology nodes
Preferred: Experience in clocking architecture, PLL/DLL architecture and design
Preferred: Expertise in timing constraint adaptation and timing closure methodologies
Preferred: Expertise in full-chip design tools and flows

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation
Hybrid work model splitting time between on-site and off-site
Mentorship
Technical leadership opportunities
Continuous learning
Collaboration within a culture that values innovation, technical excellence, and teamwork