CPU Power Management, Performance Architect

Intel Corporation

. Own power-management and performance architecture for mobile and desktop CPUs within the CPU architecture team .

Posted 10/14/2026full-timeFolsom • California • United StatesMid-LevelSenior💰 $164,470 - $311,890 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in CPU and SoC architecture, power and performance engineering, and system-level design, with a strong focus on energy efficiency and innovative techniques. Proven ability to lead cross-functional teams and communicate effectively across technical and product domains.

Highest-signal resume keywords

CPU ArchitectureSoC DesignPower And Performance EngineeringTechnical LeadershipAnalytical Problem-Solving

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

CPU MicroarchitecturePower-Management ConceptsPerformance ModelingWorkload AnalysisStatistical AnalysisFunctional ModelingBenchmarkingSilicon MeasurementsSystem-Level DesignArchitecture Design

Soft Skills

Communication SkillsCross-Functional CollaborationTechnical Tradeoff Leadership

Industry Keywords

DVFSClock GatingIdle StatesTelemetryThermal ConstraintsFirmware InteractionsOperating System InteractionsIntegrationValidationProduct Roadmaps

About the role

Key responsibilities & impact

Own power-management and performance architecture for mobile and desktop CPUs within the CPU architecture team
Define architectural capabilities and innovative techniques, guide implementation, and drive energy efficiency across operating conditions and product segments
Define and analyze CPU and SoC power and performance requirements, budgets, and interfaces across cores, shared caches, interconnects, memory, accelerators, and platform IP
Create and maintain workload-based CPU and SoC power and performance models and targets
Correlate model predictions with pre- and post-silicon data and improve current and future architectures
Partner with firmware and operating system teams on DVFS policies, clock and power gating, idle-state management, telemetry, residency, latency, and quality-of-service tradeoffs
Influence CPU microarchitecture and SoC fabric, memory, and I/O architecture to optimize power efficiency, performance, throughput, latency, and quality of service
Lead cross-functional architecture and design reviews
Drive tradeoff decisions across power, performance, area, cost, thermals, and product experience
Align CPU, SoC integration, validation, firmware, operating system, and product teams
Translate product usage models and competitive insights into architectural requirements, feature specifications, and measurable success criteria
Track execution and communicate risks, decisions, and progress to technical and product leadership

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant experience; master’s degree with 4+ years; or PhD with 2+ years
4+ years in SoC or IP architecture, CPU or SoC design, microarchitecture, power and performance engineering, or a closely related technical field
Experience may be gained through architecture, design, modeling, validation, firmware, or other closely related engineering roles
System-level thinking and ability to connect detailed design decisions to CPU, SoC, and product-level outcomes
Strong analytical problem-solving skills
Technical leadership and communication skills across CPU architecture, SoC design, firmware, validation, and product roadmaps
Extensive experience in CPU or SoC design, microarchitecture, architecture, or power and performance engineering
Experience designing, integrating, or architecting compute SoCs, CPUs, or complex silicon IP
Knowledge of CPU or SoC power-management concepts, including DVFS, clock and power gating, idle states, telemetry, thermal constraints, and firmware and operating system interactions
Advanced knowledge of computer architecture, CPU microarchitecture, system-level design, and interactions among cores, caches, interconnects, memory, accelerators, and platform IP
Experience with performance or power modeling, benchmarking, workload analysis, functional modeling, statistical analysis, or correlation of model predictions with silicon measurements
Ability to lead technical tradeoffs and communicate across design, architecture, firmware, validation, and product teams

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site and off-site