Design Verification Engineer

Intel Corporation

. Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level .

Posted 10/22/2026full-timeUnited StatesMid-LevelSenior💰 $141,910 - $200,340 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in developing and executing verification plans and testbenches, with a strong foundation in simulation-based verification methodologies and programming skills in SystemVerilog, C/C++, and Python. Proven ability to collaborate across teams and improve verification automation and quality.

Highest-signal resume keywords

SystemVerilog ProgrammingUVM/ABV MethodologiesTestbench DevelopmentAI-Assisted Development ToolsInterconnects and Bus Protocols

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Programming FundamentalsAlgorithmic Problem-SolvingC/C++ CodingPython CodingSimulation-Based VerificationDebugging SkillsCoverage-Driven VerificationVerification Code WritingAutomation Script DevelopmentFormal Verification Concepts

Soft Skills

CollaborationEffective Communication

Tools & Technologies

AI-Assisted Development Tools

Industry Keywords

InterconnectBus ProtocolsAMBA AXIPCIeCXLUCIe

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level
Build reusable verification components, checkers, constrained-random tests, and debug infrastructure
Work with architecture, design, and software teams on specification reviews, feature clarification, bug triage, and closure
Analyze simulation failures, identify root causes, and drive fixes to closure
Contribute to functional coverage planning, coverage closure, and quality signoff
Contribute to simulation and formal verification efforts
Improve verification automation, regression quality, and development efficiency

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 5+ years of industry experience OR Master's degree with 4+ years of relevant experience
Programming fundamentals and algorithmic problem-solving skills
Hands-on coding experience in SystemVerilog, C/C++, and Python
Foundation in simulation-based verification methodologies UVM/ABV
Exposure to formal verification concepts
Testbench development, debugging, and coverage-driven verification experience
Hands-on experience using AI-assisted development tools as part of daily workflow for coding, debugging, and test development
Exposure to interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, and UCIe
Proven ability to write clean, reusable, and maintainable verification code and automation scripts
Ability to collaborate effectively across architecture, design, and software teams

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between on-site and off-site work