DFT Design Engineer

Intel Corporation

. Contribute to the design and implementation of DFT solutions for complex integrated circuits .

Posted 10/13/2026full-timeJerusalem • IsraelMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in DFT solutions for integrated circuits, including RTL design, scan architecture, and mixed-signal IP DFT. Proven ability to optimize logic for test coverage and collaborate effectively with cross-functional teams on silicon verification.

Highest-signal resume keywords

DFT Solutions DesignScan ArchitectureATPG ExecutionMixed-Signal IP DFTMBIST Implementation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL CodingDFT Timing Closure SupportTest Content GenerationLogic DesignDFT IntegrationVerification Plans ReviewDebuggingTest-Coverage OptimizationVector-Memory ReductionPhysical-Implementation Goals

Certifications & Qualifications

Bachelor's Degree in Electronics Engineering

Industry Keywords

Integrated CircuitsSoCsIP-Block IntegrationSilicon VerificationDFT Activities

About the role

Key responsibilities & impact

Contribute to the design and implementation of DFT solutions for complex integrated circuits
Develop logic design, RTL coding, simulation, DFT timing closure support, and test content generation and delivery to manufacturing
Participate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT
Apply strategies, tools, and methods to generate RTL and structural code for DFT integration
Optimize logic to meet test-coverage, DPM, test-time, vector-memory reduction, and physical-implementation goals
Review verification plans and drive DFT design verification
Resolve failing RTL tests and implement corrective measures
Integrate DFT blocks into functional IP and SoCs
Support SoC customers with high-quality IP-block integration
Collaborate with post-silicon and manufacturing teams on silicon verification, debugging, and documentation
Experiment in DFT for required mixed-signal IP

Requirements

What you’ll need

Minimum Bachelor's degree in Electronics Engineering
At least 4 years of experience in DFT
Strong experience in Scan Architecture, Scan Insertion, and ATPG execution
Experience defining and implementing scan procedures
Good experience with Mixed-Signal IP DFT
Hands-on experience with MBIST implementation and MBIST validation
Experience in RTL design, DFT integration, verification, and supporting DFT activities at IP/SoC level