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E-Core CPU Layout Design Engineer
Intel Corporation. Drive the physical implementation of memory compilers, custom IP blocks, and layout partitions supporting Intel Atom microprocessors .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in physical design implementation for memory compilers and custom IP blocks, with strong collaboration skills to work effectively with cross-functional teams and drive complex digital physical design assignments.
Highest-signal resume keywords
Layout DesignVery Large Scale Integration (VLSI)Complementary Metal-Oxide Semiconductor (CMOS)UNIX Shell ScriptTCL
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Physical Design ImplementationMemory Compiler DesignCustom IP Block DesignDigital Physical DesignSchematic Interpretation
Soft Skills
Verbal CommunicationWritten CommunicationInterpersonal SkillsAnalytical SkillsProblem-Solving Skills
Tools & Technologies
CAD ToolsDebugging Tools
Industry Keywords
Electronic EngineeringMicroelectronic EngineeringComputer Engineering
Tech Stack
Tools & technologiesPerlUnix
About the role
Key responsibilities & impact- Drive the physical implementation of memory compilers, custom IP blocks, and layout partitions supporting Intel Atom microprocessors
- Assess and drive complex digital physical design assignments across multiple design stages
- Work with circuit design engineers to interpret schematics and drive physical implementation
- Collaborate with the CAD team to debug tool functionality and bugs
- Build and verify physical design hierarchy from leaf-level cell layout to block-level and top-level integration
- Partner with SoC teams and cross-site design groups to ensure alignment, reuse, and consistency across projects
Requirements
What you’ll need- Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline
- 3+ years of experience in layout design
- Less than 2 years of experience in layout design for grade 3
- Familiarity with Very Large Scale of Integration (VLSI) and Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design
- Proficient programming skills in UNIX shell script, TCL, and Perl
- Excellent verbal and written communication skills
- Excellent interpersonal skills
- Prioritization and multitasking skills
- Good analytical and problem-solving skills
Benefits
Comp & perks- Hybrid work model allowing employees to split time between working on-site at the assigned Intel site and off-site