IP Design Verification Engineer

Intel Corporation

. Build and maintain scalable, reusable UVM-based testbenches and test cases for complex mixed-signal CMOS designs at block, subsystem, and SoC levels .

Posted 9/28/2026full-timeUnited StatesJunior💰 $105,650 - $200,340 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in building and maintaining UVM-based testbenches and test cases for mixed-signal CMOS designs, along with strong capabilities in pre-silicon validation and coverage closure methodologies. Proficient in collaborating with cross-functional teams to enhance verification processes and drive results.

Highest-signal resume keywords

UVM Testbench DesignSystemVerilog AssertionsPre-Silicon ValidationDigital Design Using VerilogScripting Proficiency in Python

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

UVMSystemVerilogVerilogPre-Silicon Logic ValidationCoverage-Driven VerificationPower Verification MethodologiesEnd-to-End Validation StrategiesDebugging and TroubleshootingTest Plan DevelopmentMixed-Signal IP Verification

Soft Skills

Excellent CommunicationInterpersonal SkillsAnalytical SkillsStrong Sense of UrgencyClear Documentation

Tools & Technologies

Industry-Standard Simulation ToolsTiming and Power Convergence ToolsAI/ML Techniques for Verification Automation

Industry Keywords

Mixed-Signal CMOS DesignsSoC ArchitecturesIP ValidationPower-Aware VerificationUPF Specification

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Build and maintain scalable, reusable UVM-based testbenches and test cases for complex mixed-signal CMOS designs at block, subsystem, and SoC levels
Own and drive comprehensive verification plans and coverage closure across multiple projects
Develop RTL designs and integrate logic components into SoC architectures
Collaborate with IP providers to validate IPs at the system level
Develop and implement power verification methodologies for complex mixed-signal IPs
Create and apply SystemVerilog Assertions to improve verification quality and coverage closure
Identify, debug, and resolve pre-silicon failures and drive issues to closure
Partner with architecture, physical design, and post-silicon teams
Incorporate post-silicon learnings into enhanced pre-silicon verification methodologies
Maintain detailed test plans and lead technical reviews with design and architecture teams

Requirements

What you’ll need

Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience, or bachelor's degree in the same fields with a minimum of 3+ years of relevant experience
Experience with pre-silicon logic validation using SystemVerilog and UVM
Experience in digital design using Verilog and/or SystemVerilog
Experience with pre-silicon validation closure across multiple projects
Hands-on experience with reusable and scalable UVM testbench design
Experience with end-to-end validation strategies for complex digital systems
Experience with SystemVerilog Assertions (SVA) for coverage closure
Experience with coverage-driven verification methodologies
Scripting proficiency in Python, Perl, or TCL for design and verification automation
Self-motivated with a strong sense of urgency and commitment to delivering results
Excellent communication and interpersonal skills
Strong analytical and troubleshooting skills
Clear and concise documentation and presentation abilities
Preferred: experience in mixed-signal IP verification, UPF specification and power-aware verification, synthesizable Verilog/SystemVerilog and industry-standard simulation tools, timing and power convergence tools and methodologies, and AI/ML techniques for verification automation

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site and off-site