Memory Circuit Design Engineer

Intel Corporation

. Perform memory pathfinding activities and power, performance, and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement .

Posted 11/12/2026full-timeUnited StatesMid-LevelSenior💰 $122,440 - $232,190 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in designing and optimizing memory circuits, including SRAM and ROM, with a strong focus on power, performance, and area (PPA) trade-offs. Proficient in pre-silicon verification and post-silicon validation, leveraging EDA tools for custom digital circuit design.

Highest-signal resume keywords

Memory Circuit DesignPower, Performance, And Area (PPA) OptimizationPre-Silicon VerificationPost-Silicon ValidationDesign Technology Co-Optimization (DTCO)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Custom Memory Circuit DesignSRAM DesignRegister File DesignROM DesignDigital Circuit SimulationLayout DesignVerificationYield TrackingParametric TrackingEmbedded Memory Design

Tools & Technologies

EDA ToolsCMOS Process Technologies

Certifications & Qualifications

Master's Degree in Electrical EngineeringPhD in Electrical Engineering

Industry Keywords

Design Technology Co-Optimization (DTCO)CMOS ASIC Design FlowMemory Technology Collateral

About the role

Key responsibilities & impact

Perform memory pathfinding activities and power, performance, and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement
Design and automate memory bit-cells and complex periphery IC layouts
Design memory arrays and IP, innovate memory circuits, and design test chips
Conduct pre-silicon verification and post-silicon validation and debugging to enable yield and parametric tracking/ramp
Partner with domain experts, EDA vendors, and product design teams to develop and deliver memory technology collateral
Drive circuit innovations enabling next-generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies

Requirements

What you’ll need

Master's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, plus 4+ years of professional experience gained through internships or full-time employment, OR a PhD in one of these disciplines
Experience designing, characterizing, and verifying custom memory circuits such as SRAM, Register Files, or ROM
Knowledge of design trade-offs between power, performance, and area (PPA)
Experience with custom digital circuit design, simulation, layout design, and verification
Knowledge of EDA tools used for custom digital and memory circuit design
Preferred: PhD with 1–2 years of professional experience
Preferred: Design technology co-optimization (DTCO)
Preferred: Post-Si validation experience
Preferred: Knowledge of the CMOS ASIC design flow

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site and off-site