Pre-Silicon Verification Engineer

Intel Corporation

. Develop test benches, verification environments, and tests using System Verilog and UVM .

Posted 10/9/2026full-timeUnited StatesMid-LevelSenior💰 $122,440 - $172,860 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in System Verilog and UVM for developing test benches and verification environments, with a strong focus on functional verification of PLL and FLL clock generator IPs. Proven ability to collaborate with cross-functional teams and maintain rigorous documentation standards.

Highest-signal resume keywords

System Verilog UVM CodingDesign Verification MethodologiesFunctional VerificationScripting Languages (Python, Perl)Mixed Signal Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

System VerilogUVMFunctional VerificationDebuggingScripting (Python, Perl)Test Bench DevelopmentVerification MethodologiesAMS SimulationsMicroarchitecture SpecificationsPre-Silicon Debugging

Soft Skills

Attention to DetailProactive Problem-SolvingRoot-Cause AnalysisCollaboration

Tools & Technologies

EDA ToolsVerification Infrastructure

Industry Keywords

PLLFLLSOC ClockingRTL DevelopmentAnalog Design

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop test benches, verification environments, and tests using System Verilog and UVM
Perform functional verification for PLL and FLL clock generator IPs against microarchitecture specifications
Maintain and refine verification infrastructure and methodologies for multiple IP generations
Debug and root-cause pre-silicon issues within the verification environment
Document test plans and participate in technical reviews with design teams
Collaborate with architects, RTL developers, and analog design teams
Lead Mixed Signal Validation activities, including AMS simulations and schematic debugging
Resolve cross-functional issues
Contribute to architectural and microarchitectural feature definition and refinement for IP design

Requirements

What you’ll need

Bachelor's Degree in Electrical or Computer Engineering or a related field, with 4+ years of relevant experience; OR Master's Degree with 3+ years of relevant experience; OR PhD with 1+ years of relevant experience
2+ years of experience in design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools
2+ years of experience with scripting languages such as Python and Perl
Expertise in System Verilog UVM coding and debugging
Familiarity with PLL/FLL or SOC clocking and related RTL development
Ability to collaborate across teams including architects, RTL developers, and analog design teams
Strong attention to detail in documenting test plans and debugging pre-silicon issues
Proactive problem-solving and root-cause analysis abilities

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site and off-site