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Principal Engineer, Analog and Mixed-Signal DTCO
Intel Corporation. Lead AMS DTCO for future Intel Foundry nodes .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in Design Technology Co-Optimization (DTCO) for analog and mixed-signal designs, with a strong focus on design-rule definition, circuit benchmarking, and collaboration with EDA vendors. Proven ability to mentor engineers and lead technical direction while engaging with foundry customers and presenting findings to leadership.
Highest-signal resume keywords
DTCO ExperienceDesign-Rule DefinitionAnalog Circuit DesignEDA Tool EnablementTechnical Leadership
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Analog DesignMixed-Signal DesignCustom Layout DesignCircuit-Level Technology BenchmarkingLayout-Dependent EffectsPython AutomationMachine LearningHigh-Voltage Device IntegrationGate-All-Around TransistorsMulti-Patterning Technology
Soft Skills
MentoringTechnical EngagementPresentation Skills
Tools & Technologies
EDA ToolsLayout Generators
Industry Keywords
Semiconductor Technology DevelopmentFoundry EnvironmentsProcess NodesDevice ArchitectureQuality and Reliability
Tech Stack
Tools & technologiesNode.jsPython
About the role
Key responsibilities & impact- Lead AMS DTCO for future Intel Foundry nodes
- Evaluate device architecture, front-end and back-end design rules, metal stack, and patterning choices against analog, mixed-signal, and custom-design requirements
- Run a closed-loop DTCO process from issue sensing through prioritization, rule/PDK/flow changes, and validation on silicon and in design
- Quantify technology impact on circuits through layout studies, parasitic-aware benchmarking, and area and performance scaling analysis
- Define and drive design-rule and PDK requirements with process, design-rule, OPC, and quality and reliability teams
- Partner with EDA vendors on node enablement for custom and AMS flows
- Translate tool and flow feedback into technology decisions
- Represent Intel Foundry in technical engagements with EDA partners and foundry customers
- Present DTCO findings and recommendations to technology and business leadership
- Mentor engineers and set technical direction for the DTCO team
Requirements
What you’ll need- 5+ years of DTCO experience for analog, mixed-signal, I/O, or custom design on FinFET or more advanced process nodes
- Experience in design-rule definition for analog or custom layout, including layout-pattern studies, layout-dependent effects, and test-structure design to evaluate rule impact; or circuit-level technology benchmarking; or EDA tool or flow enablement for analog and custom design for a new process node
- Advanced degree in Electrical Engineering, Computer Engineering, Materials Science, Physics, or a related field
- Industry experience in semiconductor technology development, design enablement, or circuit design
- Master's degree with 15+ years of experience OR Ph.D. with 12+ years of experience
- Must consent to and pass an extended Background Investigation, including extended education, SEC sanctions, and additional criminal and civil checks
- Preferred: Hands-on analog, mixed-signal, or RF circuit design experience
- Preferred: Analog and RF device and passive technology knowledge
- Preferred: Experience across two or more minimum-qualification areas or across foundry and EDA environments
- Preferred: High-voltage or extended-voltage device integration on advanced CMOS nodes
- Preferred: Analog or custom layout design experience
- Preferred: Gate-all-around transistors, backside power delivery, or advanced multi-patterning technology definition knowledge
- Preferred: Automation of DTCO studies using Python, layout generators, or machine learning
- Preferred: Customer-facing technical engagement with foundry customers or EDA partners
- Preferred: Publications or patents in DTCO, design rules, design enablement, or AMS/RF circuits
- Preferred: Technical leadership across process, design, and EDA organizations
Benefits
Comp & perks- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation benefits
- Hybrid work model splitting time between working on-site at the assigned Intel site and off-site