Senior AI Systems Architect, Researcher

Intel Corporation

. Analyze AI serving and training workloads to identify communication and memory bottlenecks .

Posted 10/22/2026full-timeUnited StatesSenior💰 $195,200 - $275,580 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in AI training and inference systems, focusing on architecture design, memory hierarchy optimization, and hardware-software co-design. Proficient in C/C++ and Python, with a strong background in computer architecture and system-level design for networking and memory subsystems.

Highest-signal resume keywords

AI Training And Inference SystemsC/C++ And Python ProficiencyMemory Hierarchy OptimizationHardware-Software Co-DesignComputer Architecture And System-Level Design

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Model Architecture InternalsMemory And Data-Movement BottlenecksDisaggregated Prefill/DecodeTensor ParallelismRDMA/RoCEInfiniBandIPU/DPU/SmartNICArchitecture DefinitionSystem Bottleneck AnalysisPerformance Modeling

Soft Skills

Cross-Team Technical LeadershipInfluencing Architecture And Roadmap

Tools & Technologies

VLLMSGLangPCIeCXL

Industry Keywords

Cloud EnvironmentsHyperscale EnvironmentsNetworkingInterconnectMemory Subsystems

Tech Stack

Tools & technologies

CloudPythonC++

About the role

Key responsibilities & impact

Analyze AI serving and training workloads to identify communication and memory bottlenecks
Translate workload findings into new IP, offload engines, platform features, and architecture requirements
Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, and AI serving runtimes
Define architecture for data movement across xPUs, storage, nodes, IPU/DPU platforms, and NICs
Shape packet processing, RDMA-class transport, and programmable networking IP
Investigate KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, and communication collectives
Optimize memory hierarchy and interconnect to reduce copies, latency, and bandwidth overhead
Shape multi-generation compute, memory, and interconnect roadmaps across IPU/DPU product lines
Align architecture across networking, SoC fabric, firmware/OS/drivers, and performance modeling teams
Contribute to scientific literature, the research community, and potentially intellectual property development

Requirements

What you’ll need

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 5+ years of relevant experience; or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 2+ years of relevant experience
Experience with modern AI training and/or inference systems, including model architecture internals, hardware algorithm code design, serving runtimes, and memory and data-movement bottlenecks
Hands-on experience with vLLM, SGLang, and other inference and training serving stacks
Practical understanding of disaggregated prefill/decode, model parallelism, tensor parallelism, and related communication patterns
Experience in computer architecture and system-level design focused on networking, interconnect, or memory subsystems
Proficiency in C/C++ and/or Python
Experience with memory hierarchy and system bottleneck analysis, including caches, memory controllers, bandwidth/latency tradeoffs, and the memory wall
Experience with RDMA/RoCE, InfiniBand, or equivalent transport and interconnect
Experience with IPU/DPU/SmartNIC or accelerator-centric SoCs in cloud and hyperscale environments
Familiarity with PCIe, CXL, and memory semantics for high-performance IO
Experience defining architecture through silicon, platform software, or shipping product
Track record of cross-team technical leadership and influencing architecture and roadmap at a senior level

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation