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Senior Analog and Mixed Signal Design Engineer
Intel Corporation. Define SerDes link architecture for next-generation interfaces including 224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, and UCIe .
Core Competencies
Role fitCore Competencies
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Demonstrates expertise in high-speed wireline SerDes circuit design, including transistor-level design, link architecture, and behavioral modeling. Proven ability to lead design teams, mentor engineers, and drive design-technology co-optimization for advanced silicon processes.
Highest-signal resume keywords
Transistor-Level Design of SerDes CircuitsHigh-Speed Wireline SerDes Circuit DesignBehavioral Modeling in MATLAB or PythonLab Validation of High-Speed LinksDesign Technology Co-Optimization
ATS Keywords
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Hard Skills
SerDes Link ArchitectureChannel AnalysisLink BudgetingJitter and Noise BudgetingEqualization PartitioningTX FFERX CTLEDFEADC/DSP-Based ReceiversSilicon-Proven Design
Soft Skills
Mentoring EngineersTechnical LeadershipDesign ReviewsCollaboration with IP Partners
Tools & Technologies
MATLABPythonCOMIBIS-AMI
Industry Keywords
PAM4PCIe Gen7UCIeBER MeasurementEye Diagram AnalysisSilicon Bring-UpTape-Out ReadinessFinFETGAA CMOSSignal Integrity
Tech Stack
Tools & technologiesPython
About the role
Key responsibilities & impact- Define SerDes link architecture for next-generation interfaces including 224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, and UCIe
- Perform channel analysis, link budgeting, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers
- Build and maintain statistical and time-domain system-level link models in MATLAB or Python using COM and IBIS-AMI
- Derive block-level specifications for TX, RX, ADC, and clocking circuits
- Lead transistor-level design of critical SerDes blocks, including TX drivers, RX AFE, DFE and slicers, time-interleaved ADC front ends, CDR, phase interpolators, PLLs, and clock distribution
- Drive test-chip definition, integration, tapeout readiness, and silicon bring-up
- Correlate measured BER, eye, jitter, and power against models and lead root-cause analysis of silicon-to-model gaps
- Translate SerDes requirements into process and PDK requirements and drive design-technology co-optimization with process, PDK, and template-library teams
- Mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers
Requirements
What you’ll need- Bachelor's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design; OR Master's degree in the same fields with 4+ years of experience; OR Ph.D. in the same fields with 2+ years of experience
- Transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher
- Experience in SerDes link architecture, including channel and link-budget analysis or equalization trade-off studies used to set block-level specifications
- Lab validation of high-speed links, including BER, eye, or jitter measurement and correlation to simulation
- Behavioral or statistical link modeling in MATLAB or Python
- Preferred: Silicon-proven designs at 56 Gb/s PAM4 or higher in FinFET or GAA CMOS; multiple tape-outs with block ownership
- Preferred: Experience across architecture, lab validation, and link modeling
- Preferred: ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, 224 Gb/s-class link development, PCIe Gen6/Gen7 PHY, or UCIe die-to-die PHY development
- Preferred: Design experience on 5nm-class or more advanced nodes and design-technology co-optimization with process teams
- Preferred: Package and channel co-design, package/PCB channel modeling, signal and power integrity, and crosstalk
- Preferred: First-author publications or patents in SerDes circuits or architecture
- Preferred: Technical leadership of a multi-engineer SerDes design team through full PHY delivery
Benefits
Comp & perks- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation