Senior Design Verification Engineer

Intel Corporation

. Own verification plans for chassis and interconnect IP, prioritize functional and integration risks, and drive assigned features from initial bring-up through signoff .

Posted 11/11/2026full-timeUnited StatesSenior💰 $190,610 - $269,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in IP design verification, including high-performance interconnects and memory subsystems, while applying advanced verification methodologies such as SystemVerilog/UVM and formal verification techniques. Capable of mentoring engineers and driving verification closure through effective communication and risk management.

Highest-signal resume keywords

IP Design VerificationSystemVerilog/UVMFormal VerificationHigh-Performance InterconnectsMemory Subsystems

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogUVMPythonC/C++Assertion-Based VerificationTest AutomationFormal AbstractionEmulation-Based ValidationConfiguration-Driven RegressionsDebugging

Soft Skills

MentoringCollaborationCommunication

Tools & Technologies

AI-Assisted WorkflowsVerification InfrastructureIndependent Reference ModelsCheckers

Industry Keywords

SoC-Level VerificationCache CoherencyMemory ConsistencyTransaction OrderingIOMMUsInterrupt ControllersAMBA CHICXLPower ManagementQuality of Service

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Own verification plans for chassis and interconnect IP, prioritize functional and integration risks, and drive assigned features from initial bring-up through signoff
Build reusable environments, reference models, and checkers for data integrity, ordering, address translation, access permissions, interrupt routing and delivery, and forward progress under concurrent traffic and backpressure
Combine simulation, formal properties, and targeted experiments to find bugs and assess checker completeness, coverage gaps, and proof results
Collaborate with design and verification engineers to define interface contracts, share VIP and assertions, and debug interactions across data paths, clock and power transitions, reset sequences, and debug and trace functions
Work with architecture, design, and tooling engineers to clarify specifications, evaluate tradeoffs, and contribute reviewed changes to models, RTL, and verification infrastructure
Develop configuration-driven regressions and AI-assisted workflows for coding, property development, and debugging
Validate generated work with independent checks and reproducible tests across supported configurations
Mentor engineers through code and testplan reviews, communicate remaining risks, and establish evidence for verification closure

Requirements

What you’ll need

BS/MS in Electrical Engineering, Computer Science, or related field with 10+ years of relevant experience in design verification
Background in IP design verification with significant subsystem and SoC-level verification experience
Hands-on experience verifying high-performance interconnects and memory subsystems
Understanding of coherent, non-coherent, and I/O-coherent operation, cache coherency, memory consistency, transaction ordering, virtual memory, IOMMUs, and interrupt controllers
Experience with MESI/MOESI-based coherency mechanisms and protocols such as AMBA CHI, CXL, or comparable architectures
SystemVerilog/UVM and assertion-based verification skills
Practical experience applying formal verification alongside simulation and understanding the limits of each method
Programming and debugging skills in SystemVerilog and Python or C/C++
Ability to read RTL, build independent reference models and checkers, and develop maintainable test automation
Experience with configurable interconnect generators, generated testbenches, and verification across topology, parameter, and multi-die configurations
Experience with formal abstraction and proof decomposition, or emulation-based validation of system workloads
Experience verifying clocking, power management, reset, debug, trace, RAS, security isolation, or QoS interactions at subsystem level
Knowledge of cache hierarchies, home nodes, duplicate-tag structures, snoop filters, memory controllers, and their correctness and performance interactions
Experience building and evaluating AI-assisted engineering workflows, including checks for incorrect generated code, properties, or specification interpretations

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits