Senior DFT Design Engineer

Intel Corporation

. Perform design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG .

Posted 11/3/2026full-timeUnited StatesSenior💰 $141,910 - $172,860 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL design, validation, and automation for graphics IPs, with a strong focus on SoC integration and DFT methodologies. Proficient in using EDA tools for timing analysis and silicon enabling, ensuring high-quality GPU-block performance.

Highest-signal resume keywords

RTL DesignDFT FeaturesEDA ToolsSoC ArchitectureDesign Automation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL Code DevelopmentTiming AnalysisPattern GenerationSilicon DebugLogic OptimizationVerification PlansGraphics IP Design3D Graphics PipelinesTest Pattern DevelopmentStructural Design Flow

Tools & Technologies

Siemens TessentSynopsis VCSATPG ToolsSimulation ToolsDebug Tools

Industry Keywords

Electrical EngineeringComputer EngineeringSoC IntegrationHigh-Volume ManufacturingGraphics Engines

About the role

Key responsibilities & impact

Perform design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG
Contribute to trace and pattern generation efforts
Support post-silicon enabling, debug, and analysis of ATPG content
Develop logic designs, RTL code, and simulations for graphics IPs, including graphics, compute, display, and media
Participate in architecture and microarchitecture definition
Write RTL and optimize logic to meet power, performance, area, timing, and design-integrity goals
Review verification plans and implementations
Drive unit-level verification and resolve failing RTL tests
Support SoC customers with high-quality GPU-block integration
Design and validate next-generation graphics engines as part of Intel's GPU Hardware IP team

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM degree and 4+ years of industry experience, OR Master's degree in a related field and 3+ years of industry experience, OR PhD in a related field and 1+ years of industry experience
Experience with Scan, ATPG, or other DFT features
Experience with SoC or IP DFT design, integration, or verification
Experience with EDA tools such as Siemens Tessent, Synopsis VCS, or other ATPG, simulation, or debug tools
Silicon enabling debug or test pattern development experience
Design automation skills and proficiency in programming or scripting languages
Structural design flow experience, including timing, routing, placement, or clocking analysis
High-volume manufacturing requirements and test-flow experience
Experience with 3D, media, and display graphics pipelines
SoC architecture experience

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model splitting time between the assigned Intel site and off-site