Senior DFT Logic Design Engineer

Intel Corporation

. Provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, ATPG validation methodology, and flows .

Posted 9/15/2026full-timePhoenix • Arizona • United StatesSenior💰 $141,910 - $269,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC DFT/DFM insertion and ATPG validation methodologies, with a strong focus on customer satisfaction and effective collaboration with design teams and stakeholders. Proficient in Python, Perl, Tcl, and shell scripting to support advanced CMOS processes and ensure successful tape-outs.

Highest-signal resume keywords

ASIC DFT/DFM InsertionATPG ValidationPython ScriptingCustomer SupportCollaboration Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Advanced CMOS ProcessesDFT TimingDFT SignoffMBISTLBISTSCANJTAGShell ScriptingPerlTcl

Soft Skills

Customer-Oriented AttitudeSelf-DrivenAnalytical Problem-SolvingEffective CommunicationTeamwork Skills

Certifications & Qualifications

US CitizenshipUS Government Security Clearance

Industry Keywords

PDKsDFTDFMATPGSOC-Level DesignsBlock-Level DesignsTape-Outs

Tech Stack

Tools & technologies

PerlPythonShell Scripting

About the role

Key responsibilities & impact

Provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, ATPG validation methodology, and flows
Collaborate with internal Intel teams and external stakeholders, including customer design teams, IP providers, and EDA vendors, on issue resolution
Create content and application notes
Deliver technical training and presentations
Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for block-level and SOC-level designs
Support customer issues and challenges with tools, flows, and methodologies to enable successful customer tape-outs and increase customer satisfaction

Requirements

What you’ll need

US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
3+ years of experience with advanced CMOS processes (16nm and below)
3+ years of experience implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG, etc.) at ASIC design block level and full chip level
Experience performing ATPG validation, DFT timing, and DFT signoff at SOC level
4+ years of experience in Python, Perl, Tcl, and/or shell scripting
Customer-oriented attitude and mindset
Self-driven and results-oriented, capable of effectively working multiple tasks
Teamwork skills to drive and find solutions for customer design implementation issues/challenges
Analytical problem-solving skills
Effective communication, collaboration, listening, and feedback skills

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site and off-site
Professional development in DFT methodologies and foundry services
Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites
Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications
Direct customer engagement and technical leadership in advanced semiconductor design
Direct impact on national security through advanced semiconductor technology solutions