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Intel Corporation

Senior EDA Tools Engineer – PERC ESD

Intel Corporation

. Develop ESD/LU rule decks aligned with the ESD Design Rule Manual and reliability requirements .

Posted 10/8/2026full-timeUnited StatesSenior💰 $149,600 - $284,580 per yearWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ESD/LU rule deck development and reliability methodologies, with strong capabilities in scripting for QA automation and cross-functional collaboration. Proven ability to analyze design problems and drive innovative solutions in physical design verification.

Highest-signal resume keywords
ESD PERC Rule Deck DevelopmentScripting (Python, Tcl, Perl)Reliability/DRC ToolsPhysical Design VerificationESD/LU PreSi Models

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
ESD PERC Rule Deck DevelopmentScripting (Python)Scripting (Tcl)Scripting (Perl)Reliability/DRC ToolsTest Case DevelopmentQA Requirements DefinitionAutomation for Rule ChecksRoot Cause AnalysisDesign Rule Methodologies
Soft Skills
Analytical AbilitiesProblem-SolvingWritten CommunicationVerbal CommunicationCross-Functional Collaboration
Certifications & Qualifications
Master's Degree in Electrical EngineeringPhD in Electrical EngineeringMaster's Degree in Computer EngineeringPhD in Computer Engineering
Industry Keywords
Physical Design VerificationReliabilityDevice PhysicsProcess TechnologyDesign RulesExtractionESD/LU Verification AutomationInnovation InitiativesCross-Functional InitiativesTask Forces

Tech Stack

Tools & technologies
PerlPython

About the role

Key responsibilities & impact
  • Develop ESD/LU rule decks aligned with the ESD Design Rule Manual and reliability requirements
  • Create and maintain reliability ESD and LU design rule methodologies and specifications
  • Collaborate with internal design, reliability, and CAD teams and external EDA vendors to define and implement tool features and requirements
  • Build and execute test cases for rule debugging, validation, and signoff
  • Define QA requirements and drive automation to improve the robustness and efficiency of rule checks
  • Lead innovation initiatives to enhance ESD/LU verification automation, tools, and methodologies
  • Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions across teams

Requirements

What you’ll need
  • Master's degree or PhD in Electrical Engineering or Computer Engineering
  • 2+ years' experience with ESD PERC rule decks/runset development and debugging, or equivalent reliability/DRC tools
  • 2+ years' experience in scripting such as Python, Tcl, Perl, or similar for QA and flow automation
  • 4+ years' experience with reliability/DRC tools preferred
  • Industry experience in physical design verification, including reliability, device physics, process technology, design rules, extraction, or related domains preferred
  • Strong knowledge of ESD/LU PreSi models, including HBM and CDM, I/O design, and related methodologies preferred
  • Strong analytical and problem-solving abilities
  • Excellent written and verbal communication skills
  • Ability to work with cross-functional and cross-site teams and influence internal and external partners
  • Experience driving cross-functional and industry-wide initiatives or task forces preferred

Benefits

Comp & perks
  • Competitive pay
  • Stock bonuses
  • Health benefits
  • Retirement benefits
  • Vacation benefits