Senior FPGA IP Solutions Engineer – Robotics Technology

Intel Corporation

. Design, implement, and optimize high-performance soft IP in Verilog/SystemVerilog for robotics and industrial solutions .

Posted 10/6/2026full-timeMarlow • United KingdomSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL design and verification using Verilog/SystemVerilog for FPGA applications, with a strong focus on performance optimization, debugging, and integration within robotics systems. Proficient in utilizing industry-standard tools and methodologies for high-performance soft IP development and system validation.

Highest-signal resume keywords

RTL Design Using Verilog/SystemVerilogFPGA Design OptimizationQuartus Prime and Platform DesignerFPGA Debugging with SignalTapRobotics Software Stacks (ROS/ROS2)

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Applicant Tracking System Keywords

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Hard Skills

RTL Verification and SimulationFPGA Architecture AwarenessSensor Data Ingestion and FusionMathematical/DSP AlgorithmsStatic Timing Analysis (STA)Scripting (Tcl, Python, Perl)Low-Level HAL/Driver APIsResource Utilization OptimizationClock-Domain Crossing (CDC)Motor Control Techniques (FOC, PWM)

Soft Skills

Analytical SkillsProblem-Solving SkillsClear Written CommunicationVerbal Communication

Tools & Technologies

ModelSim/QuestaVCSPerforceGitHubJenkinsTeamCity

Industry Keywords

FPGAEmbedded SystemsRoboticsHigh-Performance Soft IPSystem Integration

Tech Stack

Tools & technologies

JenkinsPerlPython

About the role

Key responsibilities & impact

Design, implement, and optimize high-performance soft IP in Verilog/SystemVerilog for robotics and industrial solutions
Define and maintain low-level HAL/driver APIs exposing IP capabilities to embedded and host software
Develop RTL for sensor ingestion, pre-processing, fusion, and mathematical/DSP algorithms mapped to FPGA fabric
Apply FPGA architecture awareness to manage resource allocation, Fmax, and power/performance trade-offs
Integrate IP into system designs using Quartus Prime and Platform Designer, including Avalon/AXI interconnects and streaming/memory-mapped fabrics
Write and maintain testbenches; perform functional simulation and regression of IP and subsystems
Drive static timing analysis, timing closure, clock-domain crossing correctness, and constraint quality
Debug designs through simulation, SignalTap/on-chip debug, and lab bring-up
Contribute to design examples, simulation models, and technical documentation for internal and customer use
Work with Perforce, GitHub, Jenkins, and TeamCity engineering infrastructure
Support continuous integration, regression flows, and release quality for IP and reference designs
Collaborate with software, systems, and applications engineers on HW/SW co-design and platform integration, including robotics software stacks such as ROS2
Support platform bring-up, validation, and resolution of customer or internal technical issues

Requirements

What you’ll need

Minimum 10+ years of experience with BSc / MSc (or equivalent) in Electrical/Electronic Engineering (EEE), Computer Engineering, Computer Science, or a related discipline
Strong production experience in RTL design using Verilog and/or SystemVerilog targeting FPGAs
Hands-on experience with RTL verification and simulation, such as ModelSim/Questa, VCS, or equivalent
Proven ability to close timing and optimize resource utilization on real FPGA designs
Working knowledge of Quartus Prime and Platform Designer, or equivalent FPGA toolchain and system integration flows
Experience debugging FPGA designs using on-chip instrumentation, such as SignalTap Logic Analyzer, and hands-on bring-up and debug on development kits and physical boards
Familiarity with Perforce and/or GitHub, and CI systems such as Jenkins and/or TeamCity
Strong analytical, debug, and problem-solving skills, with clear written and verbal communication
Experience developing high-performance, reusable FPGA soft IP
Deep understanding of FPGA architecture, pipelining, CDC, constraints, and STA best practices
Experience with sensor data ingestion, pre-processing, sensor fusion, and/or mapping mathematical algorithms into hardware
Prior exposure to robotics systems and robotics software stacks, such as ROS/ROS2
Experience with motor control topics such as FOC, PWM generation, encoders/resolvers, current/torque loops, or real-time motion control on FPGA
Scripting experience with Tcl, Python, and/or Perl for automation of build, simulation, and timing flows
Familiarity with Avalon and/or AXI protocols, low-level HAL/driver APIs, and HW/SW integration with embedded processors or accelerators