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Senior Mixed Signal Post Silicon Validation Engineer, IO
Intel Corporation. Generate test plans and test content for mixed signal high-speed PHY post-silicon validation, including characterization of Clocking, Transmitter, and Receiver blocks .
Posted 11/9/2026full-timeFolsom • California • United StatesSenior💰 $141,910 - $200,340 per yearWebsite
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in post-silicon validation and debugging of high-speed PHYs, including PCIe, USB, and UCIe, with a strong foundation in electrical engineering principles and hands-on experience with lab hardware and software tools.
Highest-signal resume keywords
Post-Silicon ValidationHigh-Speed PHY DebuggingElectrical EngineeringMixed Signal CharacterizationSignal Integrity Knowledge
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Post-Silicon ValidationMixed Signal CharacterizationIO Protocol DebugClocking CharacterizationTransmitter CharacterizationReceiver CharacterizationRoot Cause AnalysisFailure AnalysisDebug MethodologiesPre-Silicon Design
Soft Skills
CollaborationCommunicationProblem SolvingLeadership
Tools & Technologies
OscilloscopeLogic AnalyzerProtocol AnalyzerBERT
Industry Keywords
PCIeUSBUCIeDDREthernetSilicon IssuesPower DeliverySignal IntegrityIP DebugFirmware
About the role
Key responsibilities & impact- Generate test plans and test content for mixed signal high-speed PHY post-silicon validation, including characterization of Clocking, Transmitter, and Receiver blocks
- Perform IO protocol debug across PCIe, UCIe, DDR, or Ethernet from PHY recipe and firmware perspectives
- Conduct SOC board design reviews, provide recommendations, and support post-silicon debug activities
- Represent the IP team during SOC Power-Ons for test chips and products
- Provide hands-on IP enabling support through proper recipes and firmware versions for PCIe, UCIe, and USB PHYs
- Identify clocking and PHY-related silicon issues, investigate, debug, and disposition customer bugs and sightings
- Reproduce customer issues and drive root cause analysis through failure analysis and structured debug methodologies
- Collaborate with IP design teams and SOC customers across multiple IPs and debug scenarios
Requirements
What you’ll need- BS with 6+ years, MS with 4+ years, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field
- Relevant experience in electrical or bench post-silicon validation with one or more high-speed PHYs such as PCIe, USB, UCIe, DDR, Ethernet, or equivalent interface experience
- Experience with lab hardware and software including Oscilloscopes, Logic Analyzers, Protocol Analyzers, and BERTs
- Knowledge of one or more industry-standard IO specifications such as PCIe, USB, or Die-to-Die UCIe
- Experience with mixed signal IP characterization including PLLs, TX and RX jitter characterization
- Experience leading IP debug efforts in addition to hands-on debug execution
- Signal integrity and power delivery knowledge
- Pre-silicon design or simulation experience in logic, circuits, firmware, MRC, or mixed signal validation
Benefits
Comp & perks- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation