Senior Principal Engineer

Intel Corporation

. Define and drive the architectural roadmap for FPGA compiler technologies .

Posted 9/29/2026full-timeUnited StatesSenior💰 $231,500 - $304,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in FPGA Compiler Technologies and Optimization Algorithms, with a strong focus on Timing Closure, Area Reduction, and Power Optimization. Proven ability to architect large-scale software systems and lead cross-functional teams in delivering innovative EDA solutions.

Highest-signal resume keywords

FPGA Compiler TechnologiesOptimization AlgorithmsC++ Software DevelopmentTiming AnalysisPhysical Design Methodologies

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical SynthesisLogic SynthesisPlacement and RoutingDesign Optimization AlgorithmsStatic Timing AnalysisImplementationData StructuresPerformance OptimizationMachine Learning ApplicationsPath-Based Optimization

Soft Skills

Technical LeadershipMentoringProblem SolvingCollaborationInfluencing Technical Direction

Tools & Technologies

EDA SoftwareFPGA ToolsASIC Implementation ToolsProduction Tool FlowsBenchmarking Tools

Industry Keywords

Electrical EngineeringComputer ScienceComputer EngineeringSemiconductor DesignTechnical Publications

Tech Stack

Tools & technologies

C++

About the role

Key responsibilities & impact

Define and drive the architectural roadmap for FPGA compiler technologies
Design and develop advanced optimization algorithms for timing closure, area reduction, power optimization, routability, and runtime improvement
Lead development of next-generation timing-driven optimization methodologies
Architect scalable solutions for large hierarchical designs and complex FPGA implementation flows
Drive innovation across synthesis, placement, routing, timing analysis, and physical optimization
Partner with cross-functional engineering teams to integrate new technologies into production tool flows
Analyze customer workloads, benchmark results, and field feedback to identify high-impact improvement opportunities
Lead technical investigations of challenging timing and implementation problems across customer designs
Mentor engineers and provide technical leadership across architectural and algorithmic initiatives
Collaborate with product management and strategic customers to translate market needs into differentiated technology solutions
Contribute to patents, publications, and industry-leading innovations
Influence the long-term technical direction of Altera's FPGA software platform

Requirements

What you’ll need

BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field
15+ years of experience developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies
Deep expertise in one or more of: physical synthesis, timing analysis, logic synthesis, placement and routing, design optimization algorithms, FPGA architecture and CAD flows, static timing analysis, physical design, implementation
Demonstrated experience architecting large-scale software systems and optimization engines
Strong software development skills in C++, data structures, algorithms, and performance optimization
Proven ability to solve highly complex technical problems and deliver innovative solutions to production software environments
Experience influencing technical direction across multiple engineering teams
Applicants must be eligible for any required U.S. export authorizations
Preferred: experience developing commercial FPGA or ASIC implementation tools
Preferred: expertise in path-based optimization, timing-driven synthesis, or physical design methodologies
Preferred: experience improving tool QoR, runtime performance, or scalability for large customer designs
Preferred: background creating novel optimization algorithms adopted as production technologies
Preferred: experience with machine learning applications for EDA optimization and implementation flows
Preferred: patent portfolio or significant technical publications in EDA, FPGA, or semiconductor design
Preferred: experience serving as a Distinguished Engineer, Architect, Fellow, or equivalent technical leadership role

Benefits

Comp & perks

Incentive opportunities based on individual and company performance