Senior SoC Physical Layout, Full-Chip Integration Engineer

Intel Corporation

. Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles .

Posted 9/17/2026full-timeHillsboro • Arizona • United StatesSenior💰 $122,440 - $232,190 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development, with strong skills in custom layout design and physical verification. Proficient in automation solutions using Tcl, Python, or SKILL, and capable of collaborating across engineering disciplines to drive scalable design solutions.

Highest-signal resume keywords

Full-Chip FloorplanningCustom Layout DesignPhysical Verification (DRC, LVS, DFM)Tcl, Python, SKILL AutomationAdvanced Semiconductor Technology

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Custom Layout DesignPhysical Verification DebuggingAdvanced Technology NodesFEOL Layout Design RulesTransistor-Level MatchingParasitic Layout ConceptsComplex Layout Error ResolutionDatabase ManipulationDesign Enablement for FinFETGate-All-Around Architectures

Soft Skills

Strong Ownership and AccountabilityEffective Communication SkillsCollaboration Across DisciplinesProject Planning and ExecutionProblem-Solving in Ambiguity

Tools & Technologies

CalibreICVEDA ToolsTclPythonSKILL

Certifications & Qualifications

Master's Degree in Electrical EngineeringPhD in Electrical Engineering

Industry Keywords

Silicon DevelopmentPhysical Design FlowsDesign Rule ComplianceAutomation SolutionsManufacturable Design Solutions

Tech Stack

Tools & technologies

Node.jsPython

About the role

Key responsibilities & impact

Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles
Develop and enhance custom layout methodologies and physical design flows
Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance
Collaborate with Technology Development, PDK, and EDA teams on scalable and manufacturable design solutions
Analyze advanced-node design rules and contribute to design enablement for FinFET and Gate-All-Around architectures
Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages
Coordinate cross-functional activities for tape-in readiness, database integrity, and project execution
Work across technology development, physical design, verification, and manufacturing teams
Support advanced semiconductor technology and silicon platform development

Requirements

What you’ll need

Master's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience, OR a PhD degree in the same field with 1+ years of industry experience
Custom/analog/mixed-signal layout design experience in advanced technology nodes
FEOL layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures
Physical verification debugging skills using LVS, DRC, and DFM with industry-standard verification engines such as Calibre or ICV
Proven ability to solve complex, systemic layout errors
Tcl, Python, or SKILL experience for layout automation and full-chip database manipulation
Strong ownership and accountability
Ability to make sound technical decisions with limited information
Project planning, prioritization, and execution skills
Strong collaboration and influence across engineering disciplines
Effective verbal and written communication skills
Ability to learn emerging semiconductor technologies and methodologies
Ability to navigate ambiguity and solve complex technical challenges
Continuous improvement mindset focused on automation, scalability, quality, and engineering efficiency

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model
Career development
Comprehensive employee benefits