SoC Design Verification Engineer

Intel Corporation

. Perform functional verification and emulation validation of integrated SoCs .

Posted 10/22/2026full-timeUnited StatesJunior💰 $105,650 - $149,150 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in functional verification and emulation validation of integrated SoCs, with a strong focus on developing scalable verification plans and debugging technical issues. Proficient in UVM/SystemVerilog methodologies and capable of collaborating effectively with cross-functional teams.

Highest-signal resume keywords

UVM/SystemVerilog VerificationSilicon Design ValidationDebugging SkillsScripting Languages ProficiencyCache Coherency Principles

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Functional VerificationEmulation ValidationVerification Plans DevelopmentTest Bench CreationSystem Simulation AnalysisRegression TestingValidation Test Suites DevelopmentCoverage ClosurePower Performance DebuggingPre-Silicon Environment Issues Resolution

Soft Skills

CollaborationTechnical DocumentationProblem-Solving

Tools & Technologies

Verification MethodologiesAutomation Tools

Industry Keywords

Integrated SoCsMultiprocessor SoCsPost-Silicon ValidationDesign VerificationTechnical Reviews

About the role

Key responsibilities & impact

Perform functional verification and emulation validation of integrated SoCs
Develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and environments
Execute verification plans, analyze system simulation models, and debug power and performance issues
Root-cause failure issues and implement corrective measures in the pre-silicon environment
Collaborate with architects, RTL developers, post-silicon teams, and physical design experts
Document test plans and drive technical reviews with design and architecture teams
Conduct regression and debug tests to integrate security activities and ensure comprehensive coverage
Maintain and improve verification infrastructure and methodology using learnings from post-silicon validations

Requirements

What you’ll need

Master's degree in Electrical Engineering, Computer Science or Computer Engineering
6+ months of experience in Silicon Design and/or Validation/Verification methodologies and tools
Experience with UVM/SystemVerilog constrained-random coverage-based design verification methodologies
Familiarity with the complete verification lifecycle, including test plan creation, bug debugging, and coverage closure
Skills in developing validation test suites and driving continuous improvement into existing methodologies
Understanding of cache coherency principles in multiprocessor SoCs and layered protocols
Proficiency in scripting languages for automation purposes
Strong debugging skills and ability to independently resolve technical issues
Experience with Xeon CPU pre-silicon, emulation validation, or post-silicon validation

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits