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Staff EMIB-T Substrate Yield Engineer
Intel Corporation. Own day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in yield engineering and advanced packaging technologies, with a strong focus on statistical analysis, defect reduction, and process optimization. Proficient in managing complex technical issues and collaborating across multiple organizations to drive supplier yield and manufacturing readiness.
Highest-signal resume keywords
Yield EngineeringStatistical AnalysisDefect ReductionProcess OptimizationAdvanced Packaging Technologies
ATS Keywords
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Hard Skills
Yield EngineeringStatistical AnalysisDefect ReductionProcess OptimizationFailure AnalysisSPCDFM/DFYAutomated AnalyticsImage AnalyticsComputer Vision
Soft Skills
Analytical SkillsProblem-Solving SkillsInfluencing StakeholdersManaging Complex Technical Issues
Tools & Technologies
Yield Monitoring SystemsAutomated Defect Classification SystemsDashboardsAI/ML-Based Defect Detection
Industry Keywords
Semiconductor ManufacturingSubstrate TechnologyAdvanced PackagingHVM ExecutionCross-Functional Technical Teams
About the role
Key responsibilities & impact- Own day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas
- Lead investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment
- Use statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time
- Establish supplier actions, owners, completion criteria, control limits, and verification plans
- Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics
- Capture reusable learning and communicate facts, hypotheses, decisions, and residual risks
- Drive supplier yield, defect reduction, technical issue closure, and process-control maturity for next-generation EMIB-T substrates across Taiwan suppliers
- Lead yield performance for advanced packaging technologies and support manufacturing readiness across Intel Foundry Services and Intel Product Groups
Requirements
What you’ll need- Master's degree with 4+ years or PhD with 2+ years in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline
- 4+ years of experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field
- Hands-on experience in substrate, advanced packaging, or semiconductor yield engineering
- Experience with statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution
- Strong analytical and problem-solving skills
- Experience working across multiple organizations and influencing stakeholders
- Ability to independently manage complex technical issues, execute with urgency, and drive actions to closure
- Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems
- Professional proficiency in Mandarin and English sufficient for technical work, subject to HR validation
- Preferred: experience working directly with substrate suppliers and external manufacturing partners
- Preferred: program leadership experience coordinating cross-functional technical teams
- Preferred: experience with semi-additive processing, build-up films, micro vias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration
- Preferred: prior experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies
- Preferred: experience with automated data pipelines, dashboards, image analytics, computer vision, AI/ML defect detection, or automated defect classification
Benefits
Comp & perks- Hybrid work model allowing employees to split time between working on-site at the assigned Intel site and off-site