FPGA Digital Design Engineer

Kepler Communications Inc.

. Develop custom IP for new features of Kepler satellite digital payloads .

Posted 10/16/2026full-timeRemote • Canada, United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in FPGA/RTL design, including proficiency in Verilog, SystemVerilog, and VHDL, with a strong foundation in DSP algorithms and timing principles. Capable of collaborating effectively within a team to develop advanced satellite communication systems and architectures.

Highest-signal resume keywords

FPGA/RTL DesignVerilog, SystemVerilog, VHDLXilinx FPGAs, Zynq, UltraScaleDSP Algorithms, Signal Modulation/DemodulationPython, Tcl, csh/bash Scripting

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA Design FlowTiming ClosureCoherent Digital DemodulationMemory-Mapped InterfacesHigh-Speed TransceiversPrinted Circuit Board DesignRadio-Frequency Electronics Design

Tools & Technologies

VivadoQuartusModelSimQuesta SimRiviera-Pro

Certifications & Qualifications

Bachelor’s Degree in Computer EngineeringBachelor’s Degree in Electrical EngineeringMaster of Science in Computer/Electrical Engineering

Industry Keywords

Kepler SatelliteDigital PayloadsCommunications ArchitectureEmbedded SystemsSignal Processing

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop custom IP for new features of Kepler satellite digital payloads
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors to integrate new functionality into Kepler designs
Work with lead engineers to develop communications and network architecture for the future satellite constellation
Participate in conceptual design studies of new spacecraft
Design and implement FPGA code focused on DSP algorithms for signal modulation/demodulation or embedded systems interfacing with processors and peripherals
Participate in all phases of the FPGA design flow, including simulation, synthesis, place and route, timing closure, and hardware testing
Collaborate with a small team of engineers building Kepler spacecraft

Requirements

What you’ll need

Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
5+ yr. working experience with FPGA/RTL design
Verilog, SystemVerilog, or VHDL, with willingness to learn or pivot to SystemVerilog
Experience with Xilinx FPGAs, specifically Zynq and UltraScale
Solid understanding of timing principles, including clock domain crossing and timing closure
Strong scripting skills, such as Python, Tcl, and csh/bash
Experience with FPGA tools such as Vivado and Quartus
Experience with HDL simulation tools such as ModelSim
Master of Science in Computer/Electrical Engineering or equivalent (bonus)
Experience in coherent digital demodulation of BPSK, QPSK, or QAM waveforms (bonus)
Experience with memory-mapped interfaces such as AXI, Wishbone, or Avalon (bonus)
Experience with high-speed transceivers and protocols such as JESD204B, PCIe, or SATA (bonus)
Experience with linting tools, Questa Sim, or Riviera-Pro (bonus)
Experience with Xilinx Versal and RFSoC (bonus)
Experience designing printed circuit boards (bonus)
Knowledge of radio-frequency electronics design (bonus)

Benefits

Comp & perks

Option to work from home (100% remote) available
Inclusive, accessible environment
Recruitment accommodation for applicants with disabilities
Full-time regular employment