FPGA Digital Design Engineer – Contract

Kepler Communications Inc.

. Develop custom IP for new features of Kepler satellite digital payloads .

Posted 10/23/2026full-timeRemote • Canada, United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in FPGA/RTL design, including proficiency in Verilog, SystemVerilog, and VHDL, with a strong focus on DSP algorithms for satellite communications. Capable of integrating new functionalities and improving existing designs while collaborating effectively with engineering teams.

Highest-signal resume keywords

FPGA/RTL DesignVerilogSystemVerilogXilinx FPGAsDSP Algorithms

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA Design FlowTiming ClosureSignal ModulationSignal DemodulationScripting (Python, Tcl, csh/bash)HDL SimulationModelSimVivadoQuartusClock Domain Crossing

Tools & Technologies

Xilinx ZynqXilinx UltraScaleFPGA ToolsDSPEmbedded Systems

Industry Keywords

Satellite CommunicationsDigital PayloadsSpacecraft DesignConceptual Design StudiesNetwork Architecture

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop custom IP for new features of Kepler satellite digital payloads
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors to integrate new functionality into Kepler designs
Work with lead engineers to develop communications and network architecture for the future satellite constellation
Participate in conceptual design studies of new spacecraft
Design and implement FPGA code focused on DSP algorithms for signal modulation and demodulation on software-defined radios, or embedded systems interfacing with processors and peripherals
Participate in all phases of the FPGA design flow, including simulation, synthesis, place and route, timing closure, and hardware testing
Work with a dedicated team of engineers building Kepler spacecraft

Requirements

What you’ll need

Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
5+ years of working experience with FPGA/RTL design
Experience with Verilog, SystemVerilog, or VHDL, with willingness to learn or pivot to SystemVerilog
Experience with Xilinx FPGAs, specifically Zynq and UltraScale
Solid understanding of timing principles, including clock domain crossing and timing closure
Strong scripting skills, e.g. Python, Tcl, csh/bash
Experience with FPGA tools such as Vivado and Quartus
Experience with HDL simulation tools such as ModelSim

Benefits

Comp & perks

Competitive compensation with a robust equity plan to share in our success
Comprehensive health, dental, and vision insurance coverage, including dependents
Unlimited vacation
Supportive parental leave policy
Company-wide holiday shutdown
Semi-annual company-wide parties
Frequent in-office team events
Relocation packages available for approved roles
$1,500 annual professional development fund
Fully stocked Toronto office kitchen with snacks, drinks, games and top-notch kitchen appliances
Town Halls, Celebration Calls, and Company-wide events
Great Place to Work® certification