Principal Engineer – CAD, Physical Verification

Microchip Technology Inc.

. Develop physical verification regression test cases to QA physical verification decks .

Posted 9/30/2026full-timeHsinchu • TaiwanMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in developing physical verification regression test cases and supporting layout verification activities using advanced EDA methods. Proficient in utilizing tools such as Siemens Calibre, Cadence Pegasus, and Synopsys Hercules to enhance device quality and reliability.

Highest-signal resume keywords

Physical Verification Regression Test DevelopmentSiemens CalibreCadence PegasusDebugging Physical Verification IssuesFoundry Rule Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

PDK DevelopmentSVRFTVFCalibre Interactive CustomizationCadence VirtuosoCalibreDRVAI Solutions

Soft Skills

Excellent English CommunicationInterpersonal Skills

Industry Keywords

Layout RulesDevice Identification ConceptsDesign-for-ManufacturabilityDRC RulesESDERCVoltage-Aware DRCVia Doubling Methodologies

About the role

Key responsibilities & impact

Develop physical verification regression test cases to QA physical verification decks
Support Layout and Design engineers with physical verification activities using Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
Utilize advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, and related activities
Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design-for-manufacturability checks
Develop rule decks as needed to support flow
Verify and enhance foundry rule decks
Support remote sites worldwide with layout verification activities
Support debugging of physical verification issues
Work as a team member to develop flows that improve device quality and reliability

Requirements

What you’ll need

5+ years developing and supporting PDK activities
Fluent with SVRF and TVF
Accomplished at debugging PV issues
Familiar with customizing Calibre Interactive
Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules
Strong knowledge of Cadence Virtuoso and CalibreDRV
Experience using AI solution
Excellent English verbal and written communication and interpersonal skills
Willingness to travel 0%–25%

Benefits

Comp & perks

Leadership Passage Programs supporting career growth
Employee development opportunities
Company perks
Diversity and workplace excellence programs
Travel reimbursement or other travel benefits are not specified