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Senior Engineer I – Digital Verification
Microchip Technology Inc.. Define and develop verification architecture, methodologies, and environments .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in Digital Verification, including proficiency in Verilog and System Verilog, and experience with UVM methodology. Capable of developing verification architecture, generating testbenches, and driving product verification activities to closure while mentoring junior engineers.
Highest-signal resume keywords
Digital VerificationVerilogSystem VerilogUVM MethodologyTest Plan Development
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Verification ArchitectureTestbench DevelopmentSimulation and DebuggingFunctional/Code CoverageConstrained-Random StimulusAuto-Checking VerificationIP-Level VerificationMetric-Driven VerificationUnix EnvironmentScripting Languages
Soft Skills
Strong Written CommunicationStrong Verbal CommunicationTeam CollaborationMentoring
Tools & Technologies
QuestasimVCSNCSimNCVerilogCVSGit
Industry Keywords
Mixed-Signal VerificationDigital Design FundamentalsVerification MethodologiesPost-Silicon DebuggingHigh-Performance Data Converters
Tech Stack
Tools & technologiesUnix
About the role
Key responsibilities & impact- Define and develop verification architecture, methodologies, and environments
- Write verification specifications, plans, and documentation
- Generate testbenches and automatic regression plans
- Own verification architecture, simulations, verification, and debugging of circuit and logic designs
- Complete block-level and chip-level verification
- Debug RTL for design intent and interface with cross-functional teams
- Mentor junior engineers as needed
- Present verification plans and results to the product team
- Drive product verification activities to closure using metric-driven verification methodology
- Work with the validation team on post-silicon debugging
- Contribute as a hands-on technical engineer across varied development projects for high-performance data converters and mixed-signal products
Requirements
What you’ll need- Bachelor/Master degree in Electronics or equivalent
- 5+ years of experience in Digital Verification
- Must know Verilog and System Verilog
- Experience with at least one methodology: OVM, VMM, or UVM (UVM preferred)
- Must know at least one EDA tool: Questasim, VCS, NCSim, or NCVerilog
- Good understanding of digital design fundamentals
- Proficiency with Unix environment and common scripting languages
- Expertise in test plan development
- Expertise in functional/code coverage activity
- Experience in IP-level verification activities
- Hands-on experience in coverage/assertion-driven verification
- Hands-on experience in constrained-random stimulus and auto-checking verification
- Testbench development in Verilog/SystemVerilog using verification methodology
- Strong simulation and debugging skills
- Knowledge of revision control tools such as CVS and Git
- Experience in UVM methodology
- Strong written and verbal communication skills and ability to work with geographically distributed teams
- Ability to work independently or as part of a team
- Mixed-signal verification and real-number modeling preferred
Benefits
Comp & perks- Leadership Passage Programs supporting career growth
- Employee development opportunities
- Travel time: 0%–25%