Lead Analog/Mixed-Signal ASIC Design Engineer

Mora Taara

. Lead ASIC tape-out efforts. . Own the ASIC top-level architecture. . Drive delivery and validation of ASIC dies. . Make hands-on contributions to Analog/Mixed-Signal ASIC designs. . Coordinate a small team of ASIC

Posted 11/4/2026full-timeSunnyvale • California • United StatesSenior💰 $258,000 - $294,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Analog/Mixed-Signal ASIC design and implementation, with a strong focus on high-precision and high-speed designs. Proven ability to lead ASIC tape-out efforts and coordinate engineering teams while delivering custom ASICs for integration with photonic circuits.

Highest-signal resume keywords

Ph.D. In Electrical Engineering10+ Years Industry ExperienceAnalog/Mixed-Signal Circuit DesignASIC Tape-Out LeadershipDesign Rule Checks (DRC) Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Analog/Mixed-Signal ASIC DesignHigh-Precision Design ExpertiseHigh-Speed Design ExpertiseTop-Level ASIC ArchitectureSystems-on-Chip (SoC) VerificationHardware Description LanguagesRTL Code DevelopmentTiming AnalysisPlace-and-Route Design FlowsCustom ASIC Development

Soft Skills

Excellent Communication SkillsPresentation SkillsTeam Coordination

Tools & Technologies

Design Rule Checks (DRC)Layout Versus Schematic (LVS)Power Integrity (PI) VerificationSignal Integrity (SI) VerificationVersioning Tools (SOS, Git)Commercial Layout Verification Software (Calibre)

Industry Keywords

ASIC Tape-OutPhotonic Integrated CircuitsWireless Optical Communication SystemsIntegrated Optical Phased ArraysCMOS Technologies

About the role

Key responsibilities & impact

Lead ASIC tape-out efforts.
Own the ASIC top-level architecture.
Drive delivery and validation of ASIC dies.
Make hands-on contributions to Analog/Mixed-Signal ASIC designs.
Coordinate a small team of ASIC design and layout engineers.
Own and deliver custom ASICs for co-integration with large-scale photonic integrated circuits.
Contribute to ASIC design and layout, system-level optimization, and product strategy.
Develop next-generation co-integrated electronic and photonic modules for wireless optical communication systems based on integrated optical phased arrays.

Requirements

What you’ll need

Ph.D. in Electrical Engineering or a related field.
10 or more years of relevant industry experience with demonstrated achievements in analog/mixed-signal circuit design and implementation in modern CMOS technologies.
Deep design expertise in high-precision designs and/or high-speed designs.
Experience owning top-level ASIC architecture and coordinating engineering teams.
Hands-on experience leading multiple ASIC tape-outs at commercial foundries.
Hands-on experience with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Power Integrity (PI), and Signal Integrity (SI) verification.
Experience with planning and executing verification of large Systems-on-Chip (SoCs) incorporating complex digital logic and large numbers of custom-designed blocks.
Experience with hardware description languages, RTL code, and RTL-to-GDS design flows using industry-standard EDA tools for synthesis, timing analysis, and place-and-route.
Experience with versioning tools such as SOS and Git.
Experience with commercial layout verification software (Calibre or equivalent).
Excellent communication and presentation skills, with the ability to work effectively with senior external partners.
Hands-on experience advancing a product from the prototype phase to the final production stage.

Benefits

Comp & perks

Equity
Benefits
Relocation assistance can be provided