Rack-Scale AI Hardware Architect

Mythic

. Own rack-level reference architecture covering boards, chassis, backplanes, rack topology, mechanical envelope, physical constraints, and serviceability .

Posted 9/22/2026full-timeUnited StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in rack-level architecture, including power delivery, thermal management, and interconnect design for high-density server systems. Proven ability to collaborate with software teams and validate architectures through quantitative modeling and real-world deployment.

Highest-signal resume keywords

Rack-Level Architecture OwnershipExpert Command of Copper and Optical InterconnectThermal Architecture DevelopmentPower Delivery Architecture DesignExperience with Server and Datacenter Design

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Electrical EngineeringMechanical EngineeringComputer EngineeringArchitecture and Design OwnershipPCIe InterconnectHigh-Speed EthernetThermal BudgetingPower DistributionModeling and Trade StudiesSpecification Authoring

Soft Skills

Collaborative Problem SolvingInterdisciplinary Reasoning

Tools & Technologies

Cold PlatesManifoldsCDUsHigh-Voltage DC48V-Class ConversionTelemetryRAS

Industry Keywords

HPC System DesignAI System DesignODM and OEM PartnershipsHyperscale ExperienceOCP Standards

Tech Stack

Tools & technologies

DACSwitching

About the role

Key responsibilities & impact

Own rack-level reference architecture covering boards, chassis, backplanes, rack topology, mechanical envelope, physical constraints, and serviceability
Lead architecture from pathfinding through working reference implementation
Define scale-up and scale-out interconnect, including PCIe hierarchy and switching, high-speed Ethernet and SerDes, die-to-die and board-level links, copper versus optical connectivity, retimers, connectors, cable plant, topology, oversubscription, bandwidth, and latency budgets
Develop thermal architecture for high-density racks, including direct-to-chip and cold-plate cooling, immersion, CDUs, manifolds, flow and pressure budgets, component thermal limits, and rack-to-facility interfaces
Develop power delivery architecture, including rack distribution, busbars, high-voltage DC and 48V-class conversion, efficiency, transient behavior, redundancy, telemetry, and RAS
Jointly model the full LLM solution with software teams, including partitioning strategy, inter-layer traffic, and collectives
Translate software and model requirements into fabric, memory, and topology requirements
Build quantitative rack- and cluster-level models for performance, power, thermal behavior, and cost
Deliver buildable rack reference implementations meeting performance, power, and thermal targets
Validate thermal and power architectures with measured data and support customer and partner deployment in real facilities

Requirements

What you’ll need

Minimum Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Computer Engineering, or a related field
Relevant experience in server, datacenter, HPC, or AI system design
Demonstrated architecture and design ownership of dense, rack-based server systems taken to production
Experience authoring specifications for ODM and OEM partners
Expert command of copper and optical interconnect, including PCIe, high-speed Ethernet and SerDes, DAC and twinax, backplane and cabled channels, AOCs, and pluggable or co-packaged optics
Signal-integrity judgment regarding interconnect approaches
Expert command of rack heat removal and cooling architecture, including cold plates, manifolds, CDUs, flow and thermal budgeting, and facility-side interfaces
Ability to reason across interconnect, power, thermal, mechanical, and software boundaries
Experience working with software teams on model partitioning
Track record of modeling and trade studies driving architectural decisions
Preferred: Master’s degree or PhD
Preferred: Hyperscale or OCP experience, including ORv3 and standards-body contributions
Preferred: Experience with many-small-accelerator, dataflow, or wafer-scale architectures
Preferred: Experience with LLM training or inference at scale, chiplets, die-to-die interfaces, and advanced packaging
Preferred: Experience carrying reference designs through ODM or CM partners into production and customer datacenters, including EMC, structural, and shock and vibration qualification

Benefits

Comp & perks

Inclusive team committed to candidates from all backgrounds
Senior individual-contributor role with broad organizational visibility
Direct influence on silicon, packaging, systems, software, and product strategy
Highly collaborative team environment
Outsized technical impact