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NVIDIA

DFT ATPG Engineer

NVIDIA

. Take part in state of the art Design for Test/ATPG flows and implementation .

Posted 11/9/2026full-timeTel Aviv • IsraelMid-LevelSeniorWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in Design for Test (DFT) methodologies, including ATPG, scan, and BIST, while proficient in programming languages such as TCL, PERL, and Python. Capable of collaborating with cross-functional teams to enhance automation flows and contribute to silicon bring-up processes.

Highest-signal resume keywords
Design For Test (DFT)ATPG OwnershipProgramming Skills in TCL, PERL, PythonMentor TestKompress ATPG ToolSilicon Bring-Up Experience

ATS Keywords

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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills
Programming LanguagesTCLPERLPythonUnix Shell ScriptsDFT KnowledgeATPGFault SimulationScan CompressionBIST
Soft Skills
Quick LearnerProactiveSelf-MotivatedSense of OwnershipCommitmentResponsibility
Tools & Technologies
Mentor TestKompressATE
Industry Keywords
Chip DesignBackendVerificationProduction TestingPattern Generation

Tech Stack

Tools & technologies
PerlPythonUnix

About the role

Key responsibilities & impact
  • Take part in state of the art Design for Test/ATPG flows and implementation
  • Take part in ATPG ownership on a project, from Arch & planning to pattern generation, verification and post-silicon bring up and diagnosis, while learning from experienced team members
  • Inventing and maintaining automation flows that provide the short test time to production
  • Work closely with chip design, backend, verification, and production testing groups

Requirements

What you’ll need
  • Strong programming skills in scripting languages
  • BSc. in Electrical Engineering or Computer Engineering
  • No prior work experience required
  • Quick learner, proactive and self-motivated, eager to learn and contribute, sense of ownership, commitment, and responsibility
  • Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
  • Experience in Mentor TestKompress ATPG tool and retargeting flow
  • Programming languages: TCL, PERL, Python & Unix shell scripts
  • Experience with ATE and Silicon bring-up