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NVIDIA

DFT Engineer – RDSS Intern

NVIDIA

. Verify custom IP macros . Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP, cluster, and full-chip levels .

Posted 9/29/2026full-timeTaipei • TaiwanEntry LevelWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in verification methodologies and design analysis, with a strong focus on RTL and gate-level debugging. Proficient in collaborating across teams to optimize simulation flows and develop effective test strategies.

Highest-signal resume keywords
RTL DebuggingVerification Simulation Tool (VCS)Custom IP Macros VerificationPython/Perl/Tcl/C/C++ SkillsDesign for Testing (DFT) Knowledge

ATS Keywords

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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills
RTL DebuggingGate-Level Design TracingVerification Simulation Tool (VCS)Custom IP Macros VerificationTest Pattern GenerationSilicon Bring-UpPythonPerlTclC/C++
Soft Skills
Analytical SkillsCollaborationCommunication
Tools & Technologies
VerdiSimulation Flow Optimization
Industry Keywords
SOC ArchitectureDesign for TestingScanATPGBISTJTAG

Tech Stack

Tools & technologies
PerlPythonC++

About the role

Key responsibilities & impact
  • Verify custom IP macros
  • Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP, cluster, and full-chip levels
  • Collaborate with the CAD team to optimize and smooth the simulation flow
  • Generate test patterns and perform silicon bring-up

Requirements

What you’ll need
  • Master degree of Electrical Engineering/Computer Engineering/Computer Science
  • Strong debugging and analytical skills with RTL/Gate-level design tracing (Verdi) and verification simulation tool (VCS)
  • Familiarity with SOC basic architecture (clock, reset, power rail, IO pad, package)
  • Understanding of Design for Testing including Scan/ATPG/BIST/JTAG is a plus
  • Skills of Python/Perl/Tck/C/C++ is a plus
  • Fluent English communication is required
  • Eligibility for the 2027 RDSS (Research and Development Substitute Services) program must be confirmed with the local district office