GPU/SOC Low-Power Feature Architect

NVIDIA

. Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C .

Posted 9/29/2026full-timeUnited StatesSeniorLead💰 $168,000 - $310,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in power management optimizations, high-speed interface design, and system-level debugging, with a strong foundation in electrical engineering principles. Proven ability to collaborate across diverse teams to drive the development and release of next-generation products.

Highest-signal resume keywords

Power Management OptimizationHigh-Speed Interface DesignSystem-Level DebuggingCollaboration Across TeamsElectrical Engineering Fundamentals

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Power ManagementPerformance/Power ModelingDebuggingSilicon Power ModelingFirmware/Driver InteractionTiming AnalysisStatistical Error RatesInterconnect TopologiesEnergy EfficiencyUse Case Analysis

Soft Skills

LeadershipCollaborationInfluence

Certifications & Qualifications

BS or MS Degree in Electrical EngineeringBS or MS Degree in Computer Engineering

Industry Keywords

NVLinkHigh-Speed IOsComplex InterconnectsMixed Signal DesignSystem Architecture

Tech Stack

Tools & technologies

iOS

About the role

Key responsibilities & impact

Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C
Responsible for IO power optimizations and continuing to push energy efficiency
Ensure interoperability with connected devices and system components in complex interconnect topologies
Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams
Work closely and proactively with system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design, development, debug, and release of next-generation products

Requirements

What you’ll need

BS or MS degree in EE/CE or equivalent experience
Minimum 10 years working on capacity - power management, use case analysis, perf/power modeling, bringup, and/or debug
Experience with system-level and interconnect power management optimizations
Silicon and platform-level power modeling for active/idle use cases
Understanding of firmware/driver structures and their interaction with HW
Track record of influence, leadership, and collaboration across multiple teams towards a unified goal
Strong EE fundamentals
Knowledgeable in computer architecture, high-speed interfaces, timing analysis, process variations, statistical error rates, and power analysis

Benefits

Comp & perks

Competitive salaries
Generous benefits package
Equity
Benefits