Mask Design Engineer – Hardware

NVIDIA

. Collaborate with the Package Technical Lead and design teams to design and develop detailed layouts of silicon interposers for NVIDIA products .

Posted 10/13/2026full-timeUnited StatesMid-LevelSenior💰 $108,000 - $184,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in Mask and Layout Design, with a strong command of Cadence layout tools, particularly Virtuoso. Proficient in scripting languages and experienced in design feasibility studies and custom layout verification.

Highest-signal resume keywords

Mask And Layout DesignCadence Layout ToolsScripting LanguagesDesign Feasibility StudiesSubmicron CMOS Technologies

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Mask DesignLayout DesignCustom Layout VerificationDRC CheckingLVS CheckingAuto-RoutingScripting (Perl, Python, Skill)Design Rule EvaluationPackage Layout DesignSilicon Interposer Design

Soft Skills

Interpersonal SkillsTeam CollaborationPositive EnergyPassion

Tools & Technologies

Cadence VirtuosoCalibreICVThunderAPD Package Layout Tool

Certifications & Qualifications

B.S. Electrical Engineering

Industry Keywords

Silicon InterposersPackaging TechnologyI/O Signal IntegrityDesign Feasibility StudiesSubmicron Technologies

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Collaborate with the Package Technical Lead and design teams to design and develop detailed layouts of silicon interposers for NVIDIA products
Work with design teams to plan schedules and resolve cost, manufacturing, and electrical design issues
Collaborate cross-functionally with the package technical lead, I/O signal integrity engineers, and technology engineers to deliver package solutions on tight schedules
Perform physical layout for silicon interposers using Cadence tools
Conduct design feasibility studies evaluating package goals for size, cost, and system performance
Study layout floorplans and perform custom layout and verification against design rules and netlists
Propose layout design trade-offs to the Package Technical Lead for resolution and implementation

Requirements

What you’ll need

Hold a B.S. Electrical Engineering or equivalent experience
3+ years proven experience in Mask and Layout Design
Deep understanding of layout concepts in submicron CMOS technologies
Authority with Cadence layout tools, particularly Virtuoso
Knowledge of Integrity auto-routing is a plus
Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
Proficient in scripting languages like Perl, Python, Skill, etc.
Knowledge of DRC and LVS checking flows, with ability to customize decks
Knowledge of APD package layout tool is a plus
Good understanding of packaging technology is useful
Ability to work optimally in a team, with good interpersonal skills, passion and positive energy

Benefits

Comp & perks

Equity
Benefits
Equal opportunity employment