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NVIDIA

Senior ASIC Design Engineer

NVIDIA

. Implement GPU sub-system modules .

Posted 10/5/2026full-timeUnited StatesSenior💰 $168,000 - $310,500 per yearWebsite

Core Competencies

Role fit
Core Competencies

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Demonstrates expertise in ASIC design and development, with a strong focus on micro-architecture and RTL implementation using Verilog. Proficient in digital systems, VLSI design, and post-silicon validation, complemented by strong analytical and debugging skills.

Highest-signal resume keywords
ASIC DesignMicro-ArchitectureRTL DevelopmentVerilogDigital Systems

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
ASIC DesignMicro-ArchitectureRTL DevelopmentVerilogDigital SystemsVLSI DesignTiming AnalysisPythonC/C++Debugging
Soft Skills
Interpersonal SkillsTeam CollaborationAnalytical Skills
Tools & Technologies
PCI-ExpressCXL ProtocolECOLab Debug
Certifications & Qualifications
Masters Degree in Electrical EngineeringMasters Degree in Computer Engineering
Industry Keywords
Computer ArchitectureComputer ArithmeticCMOS TransistorsLogic SynthesisPrototypingFloor-PlanningBus ProtocolsInterconnect NetworksCachesPost-Silicon Validation

Tech Stack

Tools & technologies
PerlPythonC++

About the role

Key responsibilities & impact
  • Implement GPU sub-system modules
  • Make architectural trade-offs based on features, performance requirements and system limitations
  • Own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design
  • Support post-silicon validation activities
  • Work with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams

Requirements

What you’ll need
  • Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering
  • 8+ years of proven experience working on ASIC design and development
  • Experience in micro-architecture and RTL development of complex designs in Verilog
  • Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required
  • Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
  • Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable
  • Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is very helpful; firsthand design experience is a big plus
  • Python, Perl and C/C++ programming language experience desirable
  • Good debugging and analytical skills
  • Strong interpersonal skills and ability & desire to work as a great teammate

Benefits

Comp & perks
  • Equity
  • Benefits 📊 Check your resume score for this job Improve your chances of getting an interview by checking your resume score before you apply. Check Resume Score