Senior ASIC Design Verification Engineer – LPU

NVIDIA

. Verify the design and implementation of the inference accelerator .

Posted 9/22/2026full-timeUnited StatesSenior💰 $168,000 - $310,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC design verification, including proficiency in SystemVerilog, UVM, and advanced verification methodologies. Capable of optimizing automated verification flows and collaborating effectively with cross-functional teams.

Highest-signal resume keywords

SystemVerilog ExpertiseUniversal Verification Methodology (UVM)ASIC Design VerificationAutomated Verification FlowsDesign and Verification Tools

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

ASIC Design VerificationFunctional CoverageAssertion-Based VerificationRandom Stimulus VerificationDebugging SkillsAnalytical SkillsUPF Power VerificationNetlist VerificationDFT VerificationMachine Learning Application

Soft Skills

CollaborationCommunication

Tools & Technologies

VCSVerdiPerlPythonCC++

Industry Keywords

SoC Level TestbenchVerification MethodologiesASIC Design FlowGDS

Tech Stack

Tools & technologies

PerlPythonC++

About the role

Key responsibilities & impact

Verify the design and implementation of the inference accelerator
Verify ASIC design, architecture, reference models, and micro-architecture using advanced verification methodologies
Understand unit design and implementation, define verification scope, develop verification infrastructure, and verify design correctness
Collaborate with architects, designers, and pre- and post-silicon verification teams
Implement and optimize automated verification flows to improve productivity and efficiency
Stay updated on ASIC design verification trends and incorporate innovative techniques

Requirements

What you’ll need

Bachelors Degree in EE, CS or CE (or equivalent experience)
8+ years of relevant industry experience
Background with building block and SoC level testbench utilizing strong debugging and analytical skills
Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools
Expertise in SystemVerilog and Universal Verification Methodology (UVM)
Experience with design and verification tools (VCS, Verdi or equivalent)
Knowledge of ASIC design flow, from specification to GDS
Knowledge of applying machine learning to ASIC verification flow
Background in UPF power verification is a plus
Experience in netlist and DFT verification is a plus
Perl/Python and C/C++ programming language experience desirable

Benefits

Comp & perks

Competitive salaries
Generous benefits package
Equity