Senior ASIC Timing Engineer

NVIDIA

. Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full-chip levels .

Posted 10/5/2026full-timeUnited StatesSenior💰 $136,000 - $264,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Static Timing Analysis (STA) and timing convergence for NVIDIA GPUs, CPUs, LPUs, and SoCs, with a strong background in physical design, logic synthesis, and automation methodologies. Proficient in creating timing constraints and implementing engineering change orders (ECOs) to enhance timing and power performance.

Highest-signal resume keywords

Static Timing Analysis (STA)Timing ConvergenceEngineering Change Orders (ECOs)Physical Design OptimizationDeep Sub-Micron Process Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Timing Constraints GenerationTiming Path AnalysisCrosstalk AnalysisNoise AnalysisLogic SynthesisEquivalence CheckingDFT Logic UnderstandingAutomation Methodology DevelopmentFull-Chip Timing ClosureSub-Chip Timing Closure

Soft Skills

Creative Work StyleAutonomous Work Style

Tools & Technologies

STA ToolsTiming Convergence Tools

Industry Keywords

GPUsCPUsLPUsSoCsDigital LogicAMS DesignsBISTScan

About the role

Key responsibilities & impact

Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full-chip levels
Collaborate with RTL, DFX, Clocks, and other teams to devise timing-closure strategies
Create timing constraints and drive timing and power convergence
Implement engineering change orders (ECOs)
Contribute to innovative projects and advancement of NVIDIA technology
Improve timing-convergence flows in collaboration with methodology teams

Requirements

What you’ll need

BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
Experience in physical design and optimization, including synthesis, placement, routing, and logic restructuring, to improve timing and power
Expertise and in-depth knowledge of industry standard STA and timing convergence tools
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes
Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPUs, or SoCs
Background in logic synthesis and equivalence checking/formal verification
Understanding of DFT logic and experience with DFT timing closure for scan, BIST, and other modes
Understanding and timing closure of digital logic/macros in AMS designs/IPs
Experience in methodology and/or flow development as well as automation
Creative and autonomous work style

Benefits

Comp & perks

Equity
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