Senior ASIC Timing Engineer, DFT

NVIDIA

. Drive timing analysis and closure for DFT logic on all NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip) .

Posted 11/5/2026full-timeUnited StatesSenior💰 $136,000 - $264,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Static Timing Analysis (STA) and timing convergence for DFT logic across various NVIDIA chips, with a strong focus on developing timing constraints and implementing ECOs. Proven ability to enhance workflows through automation and standardization while collaborating with cross-functional teams.

Highest-signal resume keywords

Static Timing Analysis (STA)Timing ConvergenceTiming Constraints DevelopmentECO ImplementationDFT Logic Understanding

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Timing AnalysisTiming Closure StrategiesPower ConvergenceDFT Timing ClosureAdvanced Technology NodesTiming Path AnalysisWorkflow DevelopmentAutomation TechniquesResilience ImprovementStandardization Practices

Tools & Technologies

Timing Convergence Tools

Industry Keywords

DFT LogicScanIJTAGSerdesProcessorIOSMVA

About the role

Key responsibilities & impact

Drive timing analysis and closure for DFT logic on all NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip)
Work with PD, DFX, Clocks and other teams to develop timing closure strategies
Develop timing constraints for custom DFT designs
Drive timing and power convergence
Implement ECOs
Continuously improve workflows and designs through automation, resilience, and standardization

Requirements

What you’ll need

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 2+ years’ experience
Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes
Expertise in analysis and fixing of timing paths through ECOs
Expertise in developing timing constraints
In-depth knowledge of industry standard timing convergence tools
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, iJTAG, etc. (standout qualification)
Background in domain specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc. (standout qualification)
Experience in methodology and/or workflow development (standout qualification)

Benefits

Comp & perks

Equity
Benefits
Inclusive work environment
Equal opportunity employer