Senior Mask Layout Design Engineer

NVIDIA

. Perform physical layout for mixed-signal functions including PLLs, high-speed I/O circuits, general I/Os, and ESD structure designs in innovative sub-micron CMOS technologies using Cadence tools .

Posted 10/6/2026full-timeUnited StatesSenior💰 $132,000 - $235,750 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in physical layout design for mixed-signal functions using Cadence tools, with a strong background in sub-micron CMOS technologies and extensive experience in DRC and LVS verification processes. Proven ability to collaborate with engineering teams for VLSI product integration and customization.

Highest-signal resume keywords

Physical Layout DesignCadence VirtuosoTape-Out ExperienceDRC and LVS VerificationAnalog Circuit Layout

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Mixed-Signal DesignSub-Micron CMOS TechnologiesFinFET TechnologyHigh-Speed I/O Circuit DesignSerDes Layout DesignScripting LanguagesCustom LayoutFloor PlanningVerification Against Design RulesTop Level Integration

Soft Skills

Interpersonal SkillsTeam CollaborationPositive Energy

Tools & Technologies

Cadence ToolsICVCalibre

Certifications & Qualifications

BSEEMSEE

Industry Keywords

VLSI ProductsDRC CheckingLVS CheckingAnalog Circuit Layout Concepts

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Perform physical layout for mixed-signal functions including PLLs, high-speed I/O circuits, general I/Os, and ESD structure designs in innovative sub-micron CMOS technologies using Cadence tools
Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
Perform floor planning, custom layout, and verification against design rules and schematics

Requirements

What you’ll need

Hold a BSEE or equivalent experience
MSEE is a plus
8+ years of relevant mask design / layout experience
Tape-out experience with FinFET technology is required
Experience with TSMC N5/N4/N3 is preferred
Experience with high-speed SerDes/RF layout design is helpful
Experience with top level integration would be excellent to have
Deep understanding of analog circuit layout concepts in submicron CMOS technologies
Validated experience with Cadence custom circuit design tools, particularly Virtuoso
Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre
Ability to work optimally in a team, good interpersonal skills and positive energy
Proficiency in scripting languages like Perl, Python, Skill, etc. is a plus
Knowledge of DRC and LVS checking flows
Ability to customize DRC and LVS decks

Benefits

Comp & perks

Equity
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