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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Expertise in silicon architecture and construction for next-generation CPU processors, with a strong focus on digital design, ASIC floor-planning, and advanced packaging techniques. Proven ability to collaborate with cross-functional teams to meet performance, power, and thermal objectives.
Highest-signal resume keywords
Silicon ArchitectureDigital DesignASIC Floor-PlanningAdvanced PackagingHigh-Performance Semiconductor Design
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
CPU System ArchitectureCache CoherencyHigh-Speed InterconnectsWire DensitiesDielet ConnectivityInterposer ConnectivitySubstrate ConnectivityUCIeDRAMPCIe
Soft Skills
Strong Communication SkillsInterpersonal Skills
Tools & Technologies
TSMC InFOCoWoSIntel EMIB
Certifications & Qualifications
Master’s Degree in Electrical EngineeringMaster’s Degree in Computer EngineeringMaster’s Degree in Computer Science
Industry Keywords
Processor DesignSemiconductor Design3D Hybrid-Bonded DieletDynamic Global Team
About the role
Key responsibilities & impact- Own the silicon architecture and construction plan for next-generation CPU processors
- Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including placement of IO and compute across dielets
- Develop early floorplans and plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe
- Work with architecture, logic design, physical design and packaging teams to achieve area, performance, power and thermal goals
Requirements
What you’ll need- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience
- 8+ years of experience in processor or other related high-performance semiconductor designs
- Deep understanding of digital design, CPU system architecture and ASIC floor-planning, including wire densities on-die and across 3D connected dies
- A strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols is helpful
- Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred, along with Dielet, Interposer, Substrate connectivity
- Strong communication and interpersonal skills are required
- Ability to work in a dynamic, global team
Benefits
Comp & perks- Equity
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