Senior SoC Architect, RAS

NVIDIA

. Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components .

Posted 11/6/2026full-timeUnited StatesSenior💰 $184,000 - $356,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in SoC-level RAS hardware architecture, encompassing fault detection, correction, telemetry, and recovery mechanisms. Proficient in collaborating across multidisciplinary teams to ensure robust design, verification, and validation of hardware features.

Highest-signal resume keywords

SoC ArchitectureReliability, Availability, and Serviceability (RAS)Design VerificationSilicon ValidationFault Injection

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemCC/C++PythonError HandlingDiagnostic DevelopmentResiliency ModelingCoverage AnalysisDebug VisibilityArchitecture SpecificationMicro-Architecture Alignment

Soft Skills

Analytical SkillsWritten CommunicationVerbal CommunicationInterpersonal SkillsCollaboration

Certifications & Qualifications

MS or PhD in Computer EngineeringElectrical Engineering

Industry Keywords

Functional SafetySemiconductor ReliabilityHigh-Reliability DeploymentRadiation EffectsDesign for DebugDesign for TestDesign for Reliability

Tech Stack

Tools & technologies

iOSPythonC++

About the role

Key responsibilities & impact

Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability
Collaborate with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements
Analyze interactions between RAS mechanisms and performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software
Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models in SystemC, C/C++, Python, or other relevant modeling environments
Plan and review verification and validation strategies, including error injection, recovery validation, coverage analysis, resiliency modeling, and architecture reviews
Assist with failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods
Apply RAS architecture principles to high-reliability, space-aware, and radiation-aware deployment environments
Follow industry standards and research related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing
Patent novel hardware architecture techniques that improve system resiliency, observability, serviceability, and recovery
Work with systems architects, RAS experts, design teams, verification teams, validation teams, firmware teams, and software partners

Requirements

What you’ll need

MS or PhD degree in computer engineering, electrical engineering, or equivalent experience
At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience
Strong understanding of Reliability, Availability, and Serviceability (RAS) in the SoC context, including fault detection, correction, containment, telemetry, recovery, degradation modes, debug visibility, and serviceability mechanisms
Experience defining and driving hardware architecture features through the full development lifecycle, including architecture definition, design implementation, verification planning, validation, debug, and production readiness
Strong understanding of overall SoC architecture and ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases
Meaningful industry expertise in one or more SoC architecture areas such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure
Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology
Familiarity with radiation effects, space operation, or other high-reliability deployment environments is strongly valued
Excellent analytical, written, and verbal interpersonal skills with ability to work effectively across architecture, design, verification, firmware, software, validation, and customer-facing teams
Demonstrated history of architecting and delivering complex SoC RAS features across design, verification, validation, and production phases
Deep familiarity with ECC, parity, redundancy, replay, checkpoint/restart, scrubbing, isolation, containment, telemetry, error logging, recovery flows, and graceful degradation
Experience debugging hardware failures in simulation, emulation, post-silicon validation, production, customer deployments, or other high-reliability systems
Familiarity with Design for Debug, Design for Test, Design for Reliability, silicon observability, fault-injection methodology, and coverage-driven validation flows

Benefits

Comp & perks

Equity
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