Senior System Integration Engineer, Memory

NVIDIA

. Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs .

Posted 10/31/2026full-timeUnited StatesSenior💰 $196,000 - $310,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in HBM and LPDDR system integration, characterization, and debug, with a strong focus on memory performance, power management, and reliability across silicon, package, board, and firmware. Proficient in using AI-accelerated tools for failure analysis and automating data collection and test sequencing.

Highest-signal resume keywords

HBM System IntegrationLPDDR CharacterizationSilicon BringupMemory Training BehaviorLLM-Assisted Debug

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Silicon BringupCharacterizationDebuggingMemory TrainingPower ManagementThermal ManagementTiming AnalysisSI/PI AnalysisData AutomationFailure Analysis

Soft Skills

Cross-Functional CollaborationProblem SolvingLeadership

Tools & Technologies

AI-Accelerated ToolsLLMsDebug ToolsTest Sequencing Tools

Certifications & Qualifications

BS in Electrical EngineeringMS in Electrical Engineering

Industry Keywords

HBM3JEDEC MarginsThermal-Electrical Co-SimulationECC MethodologyPHY Controller Development

About the role

Key responsibilities & impact

Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs
Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware
Translate characterization results into signed-off operating points and release criteria
Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency
Debug and resolve memory training, calibration, SI/PI, and system-level stability issues
Define validation, characterization, and issue-tracking plans across chip programs
Build frameworks ensuring appropriate tests, data collection, and issue tracking
Use AI-accelerated tools for failure-signature analysis and root-cause detection
Automate characterization data collection, test sequencing, and results analysis
Accelerate architecture exploration and cross-domain trade-off analysis using LLMs

Requirements

What you’ll need

BS or MS in EE/CE — or equivalent experience
12+ years in HBM, LPDDR, or high-speed memory systems
Hands-on depth in silicon bringup, characterization, and debug at scale
Deep command of SI/PI, timing, margining, and memory training behavior
Ability to work across design, package, firmware, validation, and product teams
Experience with HBM3/HBM3E specifics, specific JEDEC margins, thermal-electrical co-sim, ECC methodology, and power management is highly desired
PHY controller development experience is a significant plus
Familiarity with HBM PHY and controller architecture
Experience using LLM-assisted tools and ML models for debug and root cause analysis
Experience automating data collection, test sequencing, and results analysis
Experience using LLMs for architecture exploration, spec navigation, and trade-off analysis

Benefits

Comp & perks

Equity
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