Senior HW Digital Design Verification Engineer

NXP Semiconductors

. Develop and execute detailed verification plans for complex digital blocks and sub-systems, including testbench architecture, testcase development, and coverage closure.

Posted 10/6/2026full-timeSophia-Antipolis • FranceSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in developing and executing verification plans for complex digital blocks and sub-systems, utilizing advanced methodologies such as UVM and SystemVerilog. Strong background in debugging, collaborating with cross-functional teams, and mentoring junior engineers to enhance verification processes.

Highest-signal resume keywords

SystemVerilog ProficiencyUVM MethodologyDigital Design VerificationTestbench DevelopmentCoverage Analysis

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Applicant Tracking System Keywords

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Hard Skills

Digital Design VerificationTestbench DevelopmentCoverage AnalysisFormal Verification TechniquesAdvanced Verification MethodologiesScripting LanguagesDebugging SkillsTest Plans DevelopmentComplex ASICs/SoCs ExperienceComputer Architecture Understanding

Soft Skills

Problem-Solving SkillsAnalytical SkillsCommunication SkillsInterpersonal SkillsTeam Collaboration

Tools & Technologies

UVMOVMSystemVerilogEDA Verification ToolsSimulatorsWaveform ViewersCoverage Analysis ToolsPythonPerlTcl

Industry Keywords

Digital DesignVerification MethodologiesASICsSoCsDesign SpecificationsVerification EnvironmentsContinuous ImprovementTestbench ArchitectureAssertion-Based TestbenchesConstrained-Random Testing

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop and execute detailed verification plans for complex digital blocks and sub-systems, including testbench architecture, testcase development, and coverage closure.
Implement advanced verification methodologies such as UVM and formal verification techniques.
Create and maintain verification environments using industry-standard tools and languages, including SystemVerilog, UVM, OVM, and e.
Develop directed, constrained-random, and assertion-based testbenches to validate design functionality and performance.
Perform functional and code coverage analysis to ensure verification completeness.
Debug complex design and verification issues, working closely with design engineers to identify root causes and propose solutions.
Collaborate with design, architecture, and software teams to understand design specifications and requirements.
Contribute to continuous improvement of verification methodologies, flows, and tools.
Mentor junior engineers and share technical expertise within the team.

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in digital design verification of complex ASICs/SoCs.
Strong proficiency in SystemVerilog and UVM.
Demonstrated experience in developing comprehensive test plans and verification environments from scratch.
Solid understanding of digital design principles, computer architecture, and communication protocols.
Experience with industry-standard EDA verification tools, including simulators, waveform viewers, and coverage analysis tools.
Familiarity with scripting languages such as Python, Perl, and Tcl.
Experience with formal verification techniques is a plus.
Excellent problem-solving, analytical, and debugging skills.
Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.