Senior SOC Design for Test Engineer

NXP Semiconductors

. Define and implement Digital Design For Test (DFT) architectures and solutions at IP, subsystem, and SoC level .

Posted 10/6/2026full-timeValbonne • FranceSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Digital Design For Test (DFT) methodologies and architectures, with a strong focus on DFT design and verification for ASIC and SoC products. Proficient in collaborating across multidisciplinary teams to drive yield and quality improvements through effective test strategies and methodologies.

Highest-signal resume keywords

DFT Design And VerificationATPG Pattern DevelopmentDFT MethodologiesVerilog/SystemVerilogIndustry-Standard DFT Tools

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital Design FundamentalsDFT ArchitecturesScan DesignMemory BISTLogic BISTJTAGTCL ProgrammingPython ProgrammingPerl ProgrammingDebugging Skills

Soft Skills

Analytical SkillsProblem-Solving SkillsEffective CommunicationCollaboration SkillsTechnical Leadership

Tools & Technologies

Synopsys TestMAXCadence ModusSiemens TessentATE Test Development

Industry Keywords

ASICSoCSilicon Bring-UpPost-Silicon DebugSemiconductor ManufacturingAutomotive ProductsIndustrial Semiconductor Products

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Define and implement Digital Design For Test (DFT) architectures and solutions at IP, subsystem, and SoC level
Develop and integrate DFT features including Scan, ATPG, Memory BIST, Logic BIST, JTAG, and related test structures
Align DFT implementation across SoC platforms and IP blocks
Develop and execute ATPG patterns for Stuck-At, Transition Delay, Memory BIST, and Logic BIST testing
Perform DFT verification, simulations, and validation activities
Collaborate with design, verification, physical design, and product engineering teams
Support silicon bring-up and participate in post-silicon evaluation
Analyze test results, debug failures, identify root causes, and drive yield and quality improvements
Work with manufacturing and ATE teams to enable efficient production test flows
Evaluate and adopt new DFT methodologies, tools, and industry best practices
Document DFT architecture, implementation details, verification strategies, and test plans
Provide technical leadership and mentorship to junior engineers when appropriate

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field
Strong experience in DFT design and verification for complex ASIC or SoC products
Solid understanding of DFT methodologies including Scan Design, ATPG, Memory BIST, Logic BIST, and JTAG / Boundary Scan
Experience with industry-standard DFT tools such as Synopsys TestMAX, Cadence Modus, or Siemens Tessent
Good understanding of digital design fundamentals, ASIC/SoC development flows, and semiconductor manufacturing test concepts
Experience with Verilog/SystemVerilog
AI Driven programming or scripting skills using TCL, Python, Perl, or similar languages
Strong analytical and problem-solving skills
Effective communication and collaboration skills in a multidisciplinary environment
Preferred: Experience supporting silicon bring-up and post-silicon debug activities
Preferred: Experience in driving DFT conception and development with AI tools
Preferred: Familiarity with ATE test development and manufacturing test flows
Preferred: Knowledge of advanced semiconductor process technologies
Preferred: Experience working on Automotive or Industrial semiconductor products

Benefits

Comp & perks

Opportunity to work on cutting-edge SoCs
Collaboration with world-class engineering teams
Opportunity to contribute to products that make life easier, safer, and more connected