Staff DFT Engineer

Openchip

. Execute silicon design . Develop SoC DFT architecture and DFM concepts . Implement and verify DFT measures to meet product specifications and production requirements . Collaborate with design, production test, and

Posted 11/10/2026full-timeLimerick • IrelandLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in silicon design and DFT architecture, with a strong focus on implementing and verifying DFT measures to meet product specifications. Proficient in collaborating with cross-functional teams and generating test patterns to ensure compliance with production requirements.

Highest-signal resume keywords

Silicon Design ExecutionDFT Architecture DevelopmentATPG and Pattern GenerationTCL and Perl ScriptingMBIST Insertion and Scan Stitching

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT Measures ImplementationIC Digital DesignRTL DesignEDA/Simulation ToolsMBIST InsertionOCC InsertionScan StitchingATPGSimulation FlowsNetwork-on-Chip Architecture

Soft Skills

Team-OrientedCollaborativeSelf-MotivatedProblem-Solving

Tools & Technologies

TessentVCSTCLPerlMakefile

Industry Keywords

SoCMixed-Signal IPsRISC-V ISAArchitecture Analysis Tools

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Execute silicon design
Develop SoC DFT architecture and DFM concepts
Implement and verify DFT measures to meet product specifications and production requirements
Collaborate with design, production test, and qualification teams to meet test requirements
Contribute to target coverage requirements for logic, memories, IO, and mixed-signal IPs
Generate test patterns
Support post-silicon ATE and QnR
Bring up DFT, MBIST, EDT/OCC, Scan Stitching, ATPG, and simulation flows

Requirements

What you’ll need

BSc/MSc in Electrical/Electronic Engineering or a related field
10+ years of experience in IC digital design with multiple cycles of DFT and RTL design
Good knowledge of MBIST Insertion, Compression Insertion, Scan Stitching, OCC insertion, and iJTAG
Knowledge of ATPG, pattern generation, and simulation
Understanding of basic commands of EDA/simulation tools, including Tessent and VCS
Hands-on experience bringing up DFT flows using TCL, Perl, or Makefile-based scripting
Hands-on experience bringing up MBIST Insertion, EDT/OCC insertion, Scan Stitching, and ATPG/Simulation flows
Hands-on experience with TCL and Perl
Experience working in a large corporation preferred
Knowledge of Network-on-Chip architecture preferred
Knowledge of RISC-V ISA/architecture and SoCs based on this processor preferred
Knowledge of high-level digital design languages preferred
Knowledge of architecture analysis tools used for metric analysis preferred
Knowledge of Perl and Python preferred
Team-oriented, collaborative, self-starting, self-motivated, and able to solve obstacles independently

Benefits

Comp & perks

Hybrid work environment
Flexible schedule
Competitive compensation package
Opportunities for growth and career development
Diverse and inclusive work environment
Work-life balance support