Staff DFT Engineer

Openchip

. Execute silicon design . Work on SoC DFT architecture and DFM concepts . Implement and verify DFT measures to meet product specifications and production requirements . Collaborate with design, production test, and

Posted 11/10/2026full-timeBarcelona • SpainLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in silicon design, specifically in DFT architecture and implementation, with a strong focus on meeting product specifications and production requirements. Proficient in scripting languages such as TCL and Perl, and experienced in collaborating across technical teams to deliver effective DFT solutions.

Highest-signal resume keywords

DFT ArchitectureIC Digital DesignTCL ScriptingATPG and Pattern GenerationMBIST Insertion

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Silicon DesignDFT ImplementationRTL DesignMBIST InsertionCompression InsertionScan StitchingOCC InsertionIJTAGEDA ToolsSimulation

Soft Skills

Team CollaborationSelf-MotivationProblem Solving

Tools & Technologies

TessentVCSPerlPythonMakefile

Industry Keywords

SoCNetwork-on-ChipRISC-V ISAMixed-Signal IPPost-Silicon ATE

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Execute silicon design
Work on SoC DFT architecture and DFM concepts
Implement and verify DFT measures to meet product specifications and production requirements
Collaborate with design, production test, and qualification teams to meet test requirements using effective DFT solutions
Contribute to target coverage requirements for logic, memories, IO, and mixed-signal IPs
Generate test patterns
Support post-silicon ATE and QnR
Collaborate within and across teams at the technical level

Requirements

What you’ll need

BSc/MSc in Electrical/Electronic Engineering or a related field
10+ years of experience in IC digital design with multiple cycles of DFT and RTL design
Good knowledge of MBIST Insertion, Compression Insertion, Scan Stitching, OCC insertion, and iJTAG
Good knowledge of ATPG, pattern generation, and simulation
Understanding of basic commands of EDA/simulation tools, such as Tessent and VCS
Hands-on experience bringing up DFT flows using TCL, Perl, or Makefile-based scripting
Hands-on experience bringing up flows for MBIST insertion, EDT/OCC insertion, scan stitching, and ATPG/simulation
Hands-on experience with TCL and Perl scripting languages
Experience working in a large corporation preferred
Knowledge of Network-on-Chip architecture preferred
Knowledge of RISC-V ISA/architecture and SoCs based on this processor preferred
Knowledge of high-level digital design languages preferred
Knowledge of architecture analysis tools for metric analysis preferred
Knowledge of Perl and Python preferred
Team collaboration, self-motivation, self-starting attitude, and willingness to solve obstacles independently

Benefits

Comp & perks

Hybrid work environment
Flexible schedule
Competitive compensation package
Opportunities for career growth and development
Diverse and inclusive work environment
Work-life balance support